Aluminum cap for reducing scratch and wire-bond bridging of bond pads

• US 7,833,896 B2
• Filed: 09/23/2004
• Issued: 11/16/2010
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Chien-Hsiun, Wang, Chung Yu
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US10/948,073
• Publication Number:
  US 20060063365A1
• Time in Patent Office: 2,245 Days
• Field of Search: 438612-614, 257/E21.507, 257/E21.51, 257/E21.511
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method of manufacturing a semiconductor device and structure thereof. The method includes providing a workpiece, the workpiece having at least one conductive pad partially exposed through an opening in a passivation layer, the passivation layer having a top surface and the opening in the passivation layer having sidewalls. A barrier layer is formed over the at least one conductive pad, wherein the barrier layer lines the sidewalls of the opening in the passivation layer and is disposed over a top portion of the passivation layer proximate the opening. A conductive cap is formed over the barrier layer within the opening in the passivation layer, and the conductive cap is recessed to a height below the top surface of the passivation layer. The conductive cap may be used for testing with a probe or may be used for wire-bonding.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece, the workpiece having at least one conductive pad with an overlying passivation layer;

forming an opening in the passivation layer, thereby at least partially exposing the at least one conductive pad, the passivation layer having a top surface and the opening in the passivation layer having sidewalls;

forming a barrier layer over the at least one conductive pad, wherein the barrier layer lines the sidewalls of the opening in the passivation layer and is disposed over a top portion of the passivation layer proximate the opening such that the barrier layer has a top surface over the top surface of the passivation layer;

forming a conductive cap over the barrier layer within the opening in the passivation layer, the conductive cap completely filling the opening; and

recessing the conductive cap to a height below the top surface of the passivation layer and the top surface of the barrier layer.

2. The method according to claim 1, wherein recessing the conductive cap comprises an isotropic etch process.

3. The method according to claim 1, wherein recessing the conductive cap comprises a spray wet etch process.

4. The method according to claim 1, wherein recessing the conductive cap comprises an etch process using H₃PO₄ or HNO₃.

5. The method according to claim 4, wherein the etch process comprises H₃PO₄ or HNO₃ acid at a concentration of about 12% to 25% with deionized water.

6. The method according to claim 4, wherein the etch process comprises a temperature of about 25 to 95°

C.

7. The method according to claim 4, wherein the etch process comprises a time of about 60 to 300 seconds.

8. The method according to claim 1, wherein forming the conductive cap comprises forming aluminum, and wherein the at least one conductive pad comprises copper.

9. The method according to claim 1, wherein forming the conductive cap comprises forming about 2 μ

m or less of aluminum, and wherein recessing the conductive cap comprises recessing the conductive cap to a height of about 5000 Å

or less below the top surface of the passivation layer.

10. The method according to claim 1, wherein forming the barrier layer comprises forming TaN or TiN.

11. The method according to claim 1, wherein forming the barrier layer comprises forming a material layer having a thickness of about 2000 Å

or less.

12. The method according to claim 1, further comprising bonding a wire to the conductive cap disposed over each at least one conductive pad.

13. The method according to claim 1, wherein forming the barrier layer and forming the conductive cap comprise:

depositing a barrier layer material over the workpiece;

depositing a conductive cap material over the barrier layer material; and

patterning the conductive cap material and the barrier layer material using a single lithography mask.

14. The method according to claim 13, further comprising polishing the conductive cap material using a chemical mechanical polish (CMP) process, before or after patterning the conductive cap material and the barrier layer material.