Simultaneous conditioning of a plurality of memory cells through series resistors

• US 7,834,384 B2
• Filed: 04/02/2008
• Issued: 11/16/2010
• Est. Priority Date: 04/07/2006
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Furukawa, Toshijaru, Koburger, Charles W. III, Hakey, Mark C., Horak, David V., Lam, Chung H., Holmes, Steven J., Meijer, Gerhard I.
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): Kim; Sun M
• Application Number:
  US12/060,922
• Publication Number:
  US 20080185652A1
• Time in Patent Office: 958 Days
• Field of Search: 438/3, 257/295, 257/E27.104
• US Class Current: 257/295
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Claims

1. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:

multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and

,

a series resistor temporarily connected in series to said second electrodes, wherein said series resistor is configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements.

2. The semiconductor structure of claim 1, wherein a size of said temporary series resistor is predetermined based on the output capacity of the power supply used to apply said current in order to ensure that said current is applied equally to each of said memory elements.

3. The semiconductor structure of claim 1, wherein said temporary series resistor comprises a temporary resistive layer-metal layer stack adjacent to said memory elements such that a resistive layer of said stack contacts said second electrodes.

4. The semiconductor structure of claim 1, wherein said temporary series resistor comprises an electrolyte solution that is contained over said memory elements such that said electrolyte solution contacts said second electrode of each of said memory elements, wherein said electrolyte solution has selected conductive and resistive properties.

5. The semiconductor structure of claim 1, wherein said temporary series resistor comprises mercury that is contained over said memory elements such that said mercury contacts said second electrode of each of said memory elements.

6. The semiconductor structure of claim 1, wherein said temporary series resistor comprises a plasma that is contained over said memory elements such that said plasma contacts said second electrode of each of said memory elements, wherein said plasma has selected conductive and resistive properties.

7. The semiconductor structure of claim 1, further comprising additional series resistors electrically connected to said first electrodes of said memory elements to further limit said current passing through said memory elements.

8. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:

multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes;

series resistors electrically connected in series to corresponding first electrodes of said memory elements, wherein said series resistors are configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements; and

a temporary series resistor electrically connected to said second electrodes to further limit said current passing through said memory elements.

9. The semiconductor structure of claim 8, wherein each of said memory cells comprises a diffusion region with a first conductivity type that contacts a corresponding first electrode and a semiconductor substrate with a second conductivity type below said diffusion region,

wherein each of said series resistors comprises a semiconductor well with said second conductivity type that connects said semiconductor substrate and said diffusion region, and

wherein said semiconductor well has less of a second conductivity type dopant than said semiconductor substrate and, thereby, functions as a resistor.

10. The semiconductor structure of claim 8, wherein a size of said temporary series resistor is predetermined based on the output capacity of the power supply used to apply said current in order to ensure that said current is applied equally to each of said memory elements.

11. A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:

forming a series resistor over said memory elements such that said series resistor contacts said second electrodes of said memory elements;

simultaneously applying current to said memory elements so as to simultaneously condition said transition metal oxide in each of said memory elements, wherein said series resistor limits said current passing through said memory elements to avoid damaging said transition metal oxide; and

removing said series resistor.

12. The method of claim 11, wherein a size of said series resistor is predetermined based on the output capacity of the power supply used for said applying of said current in order to ensure that said current is applied equally to each of said memory elements.

13. The method of claim 11, wherein said forming of said series resistor comprises forming a resistive layer-metal layer stack over said memory elements such that a resistive layer of said stack contacts said second electrodes, and

wherein said applying of said current comprises supplying said current to said temporary metal layer.

14. The method of claim 11, wherein said forming of said series resistor comprises forming an electrolyte solution, having selected conductive and resistive properties, and containing said electrolyte solution over said memory elements such that said electrolyte solution contacts said second electrodes, and

wherein said applying of said current comprises supplying said current to said electrolyte solution.

15. The method of claim 11, wherein said forming of said series resistor comprises containing mercury over said memory elements such that said mercury contacts said second electrode of each of said memory elements, and

wherein said applying of said current comprises supplying said current to said mercury.

16. The method of claim 11, wherein said forming of said series resistor comprises forming a plasma, having selected conductive and resistive properties, and containing said plasma over said memory elements such that said plasma contacts said second electrodes, and

wherein said applying of said current comprises supplying said current to said plasma.

17. The method of claim 11, further comprising forming additional series resistors within said memory cells such that said additional series resistors contact said first electrodes of said memory elements to further limit said current passing through said memory elements.