Low voltage, two-level, six-pulse induction motor controller driving a medium-to-high voltage, three-or-more-level AC drive inverter bridge

• US 7,834,579 B2
• Filed: 07/31/2003
• Issued: 11/16/2010
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Nojima, Geraldo
• Primary Examiner(s): IP, SHIK LUEN PAUL
• Application Number:
  US10/522,792
• Publication Number:
  US 20060197491A1
• Time in Patent Office: 2,665 Days
• Field of Search: 318/254.2, 318/800, 318/801, 388/811, 388/812, 363/37, 363/71, 363/98, 363/132
• US Class Current: 318/801
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/53876 based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times
• CPC Class Codes: H02P 27/14 with three or more levels of voltage

Abstract

A method and circuit enabling off-the-shelf controllers designed for use with a two-level AC drive inverter bridge (1920) to drive inverter bridges with three-or-more levels. Signals from an ordinary induction motor controller or a two-level induction motor controller (2200) are used to drive the twelve-or-more switches of a three-or-more level inverter bridge (1920), as are used in medium-and-high voltage applications. The proper sequence and timing of switching for the three-or-more-level inverter bridge is based in-part upon either the output of the six pulse-width modulators, or the output of the flux and torque control device, or the voltage control device (2210), of the two-level controller (2200).

Claims

1. A method of controlling a multiple-level inverter bridge with a two-level induction motor controller, the two-level induction motor controller outputting six modulated signals for controlling switching of six switches in a two-level inverter bridge, said method comprising:

converting the six modulated signals into N time-coordinated signals, wherein N≧

12 and N is an integer-multiple of 3;

controlling N switches of the multiple-level inverter bridge by applying the N time-coordinated signals,

wherein the multiple-level inverter bridge comprises three branches, each branch having N/3 switches and producing one phase of a three-phase output of the multiple-level inverter bridge, and never-less-than N/6 of the N/3 switches of a respective branch of the multiple level inverter bridge having a logical-off state.

2. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 1,

wherein the six modulated signals are further characterized as being three pairs of modulated signals A_1b and A_2b (bε

{1, 2, 3}), each pair of modulated signals intended for controlling one-of-three branches of a two-level inverter bridge, each branch b producing one phase of a three-phase output of a two-level inverter bridge;

said step of converting the six modulated signals into N time-coordinated including;

generating three sets of time-coordinated signals S_1b to S_(N/3)b from the three pairs of modulated signals A_1b and A_2b output by the two-level induction motor controller, each set of time-coordinated signals S_1b to S_(N/3)b being timed to control the switches of branch b of the multiple-level inverter bridge, timing of each set of time-coordinated signals S_1b to S_(N/3)b varying based on at least a delay time of the switches of the respective branch b, and for each branch b, never-less-than N/6 of the time-coordinated signals S_1b to S_(N/3)b having a logical-off state; and

said step of controlling said N switches of the multiple-level inverter bridge including;

applying each set b of time-coordinated signals S_1b to S_(N/3)b to the N/3 switches of a corresponding branch b of the multiple-level inverter bridge.

3. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 2, said step of generating three sets of time-coordinated signals S_1b to S_(N/3)b from the three pairs of modulated signals A_1b and A_2b comprising:

for time-coordinated signals S_1b to S_(N/6)b, forming each S_yb to have a logical-on state after, and a logical-off state before, S_(y+1)b, y being a series of integers from 1 to (N/6−

1), and

for time-coordinated signals S_(N/6+1)b to S_(N/3)b, forming each S_zb to have a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

4. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 2, said step of generating the three sets of time-coordinated signals S_1b to S_(N/3)b from the three pairs of modulated signals A_1b and A_2b comprising:

forming time-coordinated-signals S_1b to S_(N/6)b by adding a turn-on delay d_1x·

Δ

t_b, and a turn-off delay d_2x·

Δ

t_b, to the modulated signal A_1b; and

forming time-coordinated signals S_(N/3)b to S_(N/6+1)b by adding a turn-on delay d_1x·

Δ

t_b, and a turn-off delay d_2x·

Δ

t_b, to the modulated signal A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of N/3 switches in a branch b of the multiple-level inverter bridge, d_1x≧

0, d_2x≧

0, and x=1 to N/6, and

wherein every d_1x has a different value, and every d_2x has a different value.

5. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 4,

wherein for time-coordinated signals S_1b to S_(N/6)b, each S_yb has a logical-on state after, and a logical-off state before, S_(y+1)b, y being a series of integers from 1 to (N/6−

1), and

wherein for time-coordinated signals S_(N/6+1)b to S_(N/3)b, each S_zb has a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

6. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 2,

wherein the multiple-level inverter has three levels and N=12, each branch b of the three-level inverter comprising four switches connected in series and controlled by time-coordinated signals S_1b-S_4b;

and

said step of generating the three sets of time-coordinated signals S_1b-S_4b from the three pair of modulated signals A_1b and A_2b comprising;

forming time-coordinated signal S_1b by adding a turn-on delay of 3Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_2b by adding a turn-on delay of Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_3b by adding a turn-on delay of Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_4b by adding a turn-on delay of 3Δ

t_b to the modulated signal A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of the four switches in the respective branch b.

7. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 2,

wherein the multiple-level inverter has four levels and N=18, each branch b of the four-level inverter comprising six switches connected in series and controlled by time-coordinated signals S_1b-S_6b;

and

said step of generating the three sets of time-coordinated signals S_1b-S_6b from the three pair of modulated signals A_1b and A_2b comprising;

forming time-coordinated signal S_1b by adding a turn-on delay of 5Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_2b by adding a turn-on delay of 3Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_3b by adding a turn-on delay of Δ

t_b and a turn-off delay of 4Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_4b by adding a turn-on delay of Δ

t_b and a turn-off delay of 4Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_5b by adding a turn-on delay of 3Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_6b by adding a turn-on delay of 5Δ

t_b to the modulated signal A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of the six switches in the respective branch b.

8. The method of controlling a multiple-level inverter bridge with a two-level induction motor controller as defined in claim 2,

wherein the multiple-level inverter has five levels and N=24, each branch b of the five-level inverter comprising eight switches connected in series and controlled by time-coordinated signals S_1b-S_8b;

and

said step of generating the three sets of time-coordinated signals S_1b-S_8b from the three pair of modulated signals A_1b and A_2b comprising;

forming time-coordinated signal S_1b by adding a turn-on delay of 7Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_2b by adding a turn-on delay of 5Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_3b by adding a turn-on delay of 3Δ

t_b and a turn-off delay of 4Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_4b by adding a turn-on delay of Δ

t_b and a turn-off delay of 6Δ

t_b to the modulated signal A_1b;

forming time-coordinated signal S_5b by adding a turn-on delay of Δ

t_b and a turn-off delay of 6Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_6b by adding a turn-on delay of 3Δ

t_b and a turn-off delay of 4Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_7b by adding a turn-on delay of 5Δ

t_b and a turn-off delay of 2Δ

t_b to the modulated signal A_2b;

forming time-coordinated signal S_8b by adding a turn-on delay of 7Δ

t_b to the modulated signal A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of the eight switches in the respective branch b.

9. An adapter circuit for controlling a multiple-level inverter bridge with a two-level induction motor controller, the two-level induction motor controller outputting six modulated signals for controlling switching in a two-level inverter bridge, and the multiple-level inverter bridge having N≧

12 switches divided into 3 branches, the adapter circuit, comprising;

three pairs of modulated signal inputs A_1b and A_2b (bε

={1, 2, 3}), whereby the six modulated signals from the two-level induction motor controller are input;

three sets of time-coordinated signal outputs S_1b to S_(N/3)b, wherein each set b of time-coordinated signals output via S_1b to S_(N/3)b is timed to control N/3 switches of branch b of the multiple-level inverter bridge; and

timing circuitry comprising circuitry selected from the group consisting of combinatorial circuits, sequential circuits, delay elements, analog-based logic gates, programmable logic, and a combination thereof, generating time-coordinated signals output via S_1b to S_(N/6)b from modulated signals input via A_1b, and generating time-coordinated signals output via S_(N/6+1)b to S_(N/3)b from modulated signals input via A_2b, adding at least a turn-on delay or turn-off delay to each modulated signal input via A_1b and A_2b,

wherein for each set b of time-coordinated signals output via S_1b to S_(N/3)b, never-less-than N/6 of the N/3 time-coordinated signals has a logical-off state.

10. The adapter circuit as defined in claim 9,

wherein for time-coordinated signals output via S_1b to S_(N/6)b, each S_yb has a logical-on state after, and a logical-off state before, S_(y+1)b, y being a series of integers from 1 to (N/6−

1), and

wherein for time-coordinated signals output via S_(N/6+1)b to S_(N/3)b, each S_zb has a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

11. The adapter circuit as defined in claim 9,

wherein within each set b of time-coordinated signals output via S_1b to S_(N/3)b:

each time-coordinated signal output via S_1b to S_(N/6)b is formed by adding a turn-on delay d_1x·

Δ

t_b and a turn-off delay d_2x·

Δ

t_b to the modulated signal input via A_1b; and

each time-coordinated signal output via S_(N/3)b to S_(N/6+1)b is formed by adding a turn-on delay d_1x·

Δ

t_b and a turn-off delay d_2x·

Δ

t_b, to the modulated signal input via A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of N/3 switches in a branch b of the multiple-level inverter bridge, d_1x≧

0, d_2x≧

0, and x=1 to N/6, and

wherein every d_1x has a different value, and every d_2x has a different value.

12. The adapter circuit as defined in claim 11,

wherein for time-coordinated signals output via S_1b to S_(N/6)b, each S_yb has a logical-on state after, and a logical-off state before, S_(y+1)b, y being a series of integers from 1 to (N/6−

1), and

wherein for time-coordinated signals output via S_(N/6+1)b to S_(N/3)b, each S_zb has a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

13. The adapter circuit as defined in claim 11, wherein N=12, d₁₁=3, d₁₂=1, d₂₁=0, and d₂₂=2.

14. The adapter circuit as defined in claim 11, wherein N=18, d₁₁=5, d₁₂=3, d₁₃=1, d₂₁=0, d₂₂=2, and d₂₃=4.

15. The adapter circuit as defined in claim 11, wherein N=24, d₁₁=7, d₁₂=5, d₁₃=3, d₁₄=1, d₂₁=0, d₂₂=2, d₂₃=4, and d₂₄=6.

16. The adapter circuit as defined in claim 9, said combinatorial circuits comprising AND and OR gates, and said sequential circuits comprising flip-flops.

17. The adapter circuit as defined in claim 9, wherein said adapter circuit comprises a Complex Programmable Logic Device.

18. An adapter for controlling a multiple-level inverter bridge with a two-level induction motor controller, the two-level induction motor controller outputting six modulated signals for controlling switching in a two-level inverter bridge, and the multiple-level inverter bridge having N≧

12 switches divided into 3 branches, the adapter, comprising;

three pairs of modulated signal inputs A_1b and A_2b (bε

{1, 2, 3}), whereby the six modulated signals from the two-level induction motor controller are input;

three sets of time-coordinated signal outputs S_1b to S_(N/3)b, wherein each set b of time-coordinated signals output via S_1b to S_(N/3)b is timed to control N/3 switches of branch b of the multiple-level inverter bridge; and

first conversion means for generating time-coordinated signals output via S_1b to S_(N/6)b from a modulated signals input via A_1b, adding at least a turn-on delay or turn-off delay to generate S_1b to S_(N/6)b from the modulated signal input via A_1b,

second conversion means for generating time-coordinated signals output via S_(N/6+1)b to S_(N/3)b from a modulated signal input via A_2b, adding at least a turn-on delay or turn-off delay to generate S_(N/6+1)b to S_(N/3)b from the modulated signal input via A_2b,

wherein for each set b of time-coordinated signals output via S_1b to S_(N/3)b, never-less-than N/6. of the N/3 time-coordinated signals has a logical-off state.

19. An induction motor drive system for driving a three-phase motor, comprising:

a two-level induction motor controller, outputting signals for controlling a two-level inverter bridge;

a multiple-level inverter bridge, having N≧

12 switches arranged to form 3 branches, each branch providing one phase of a three-phase output for driving the three-phase motor; and

an adapter circuit, generating N time-coordinated signals controlling the N switches of the multiple-level inverter bridge from said signals output by the two-level induction motor controller.

20. The induction motor drive system as defined in claim 19,

wherein the signals output from the two-level induction motor controller comprise three pairs of modulated signal inputs A_1b and A_2b (bε

{1, 2, 3 }), intended for controlling switching in a two-level inverter bridge; and

wherein the N-time coordinated signals are further characterized as being three sets of time-coordinated signals S_1b to S_(N/3)b, each set being timed to control the N/3 switches of branch b of the multiple-level inverter bridge, and within each set b, never-less-than N/6 of the time-coordinated signals S_1b to S_(N/3)b having a logical-off state; and

wherein the adapter circuit comprises circuits selected from the group consisting of combinatorial circuits, sequential circuits, delay elements, analog-based logic gates, programmable logic, and a combination thereof generating the time-coordinated signals S_1b to S_(N/6)b from the modulated signal A_1b, and timing circuitry generating time-coordinated signals S_(N/6+1)b to S_(N/3)b from the modulated signal A_2b, forming S_1b to S_(N/3)b by adding at least a turn-on delay or turn-off delay to the modulated signal A_1b and A_2b.

21. The induction motor drive system as defined in claim 20,

wherein for time-coordinated signals S_1b to S_(N/6)b, each S_yb has a logical-on state after, and a logical-off state before, S_(y+1)b, y being a series of integers from 1 to (N/6−

1), and

wherein for time-coordinated signals S_(N/6+1)b to S_(N/3)b, each S_zb has a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

22. The induction motor drive system as defined in claim 20,

wherein within each set b of time-coordinated signals S_1b to S_(N,3)b:

each time-coordinated signal S_1b to S_(N/6)b is formed by adding a turn-on delay d_1x·

Δ

t_b and a turn-off delay d_2x·

Δ

t_b to the modulated signal A_1b; and

each time-coordinated signal S_(N/3)b to S_(N/6+1)b is formed by adding a turn-on delay d_1x·

Δ

t_b and a turn-off delay d_2x·

Δ

t_b, to the modulated signal A_2b;

wherein Δ

t_b is a turn-off delay time of a switch with a longest turn-off delay time of N/3 switches in a branch b of the multiple-level inverter bridge, d_1x≧

0, d_2x≧

0, and x=1 to N/6, and

wherein every d_1x has a different value, and every d_2x has a different value.

23. The induction motor drive system as defined in claim 22,

wherein for time-coordinated signals S_1b to S_(N/6)b, each S_yb has a logical-on state after, and a logical-off state before, S^(y+1)b, y being a series of integers from 1 to (N/6−

1), and

wherein for time-coordinated signals S_(N/6+1)b to S_(N/3)b, each S_zb has a logical-on state after, and a logical-off state before, S<sub>(z−

1)b</sub>, z being a series of integers from (N/6+2) to (N/3).

24. The induction motor drive system as defined in claim 19,

wherein the signals output from the two-level induction motor controller comprise three pairs of modulated signal inputs A_1b and A_2b (bε

{1, 2, 3}), intended for controlling switching in a two-level inverter bridge; and

wherein the N-time coordinated signals are further characterized as being three sets of time-coordinated signals S_1b to S_(N/3)b, each set being timed to control the N/3 switches of branch b of the multiple-level inverter bridge, and within each set b, never-less-than N/6 of the time-coordinated signals S_1b to S_(N/3)b having a logical-off state; and

wherein the adapter circuit comprises;

first conversion means for generating time-coordinated signals output via S_1b to S_(N/6)b from a modulated signals input via A_1b, adding at least a turn-on delay or turn-off delay to generate S_1b to S_(N/6)b from the modulated signal input via A_1b, and

second conversion means for generating time-coordinated signals output via S_(N/6+1)b to S_(N/3)b from a modulated signal input via A_2b, adding at least a turn-on delay or turn-off delay to generate S_(N/6+1)b to S_(N/3)b from the modulated signal input via A_2b.

25. A method of controlling a multiple-level inverter bridge with a two-level induction motor controller, the two-level induction motor controller comprising a regulator and an internal modulator for a two-level inverter bridge, command signals being output from the regulator for control of the internal modulator, the method comprising:

outputting the command signals from the two-level induction motor controller via a first interface port of the two-level induction motor controller;

transmitting the command signals output from said first interface port via a serial or parallel connection;

inputting the transmitted command signals into an external adapter circuit via a second interface port, said adapter circuit comprising a modulator; and

generating, in the modulator of the external adapter circuit and based on the command signals input via said second interface port, twelve-or-more time-coordinated signals for controlling an inverter bridge having three-or-more levels.

26. The method of controlling a multiple-level inverter bridge as defined in claim 25, further comprising:

controlling twelve-or-more switches in a multiple-level inverter bridge by applying the twelve-or-more time-coordinated signals generated by the modulator of the external adapter circuit.

27. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein said steps of outputting, transmitting, and inputting result in updated command signals being periodically provided to the external adapter circuit.

28. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the two-level induction motor controller utilizes vector control, said regulator being a flux and torque regulator and said command signals output from the two-level induction motor controller being flux (d) and torque (q) command signals.

29. The method of controlling a multiple-level inverter bridge as defined in claim 28, said method further comprising:

transforming the flux (d) and torque (q) command signals into α and

β

command signals via a Park Transform, after inputting the transmitted command signals into the external adapter circuit, but before generating the twelve-or-more time coordinated signals in the modulator, said modulator of the external adapter circuit generating the twelve-or-more time coordinated signals using the α and

β

command signals.

30. The method of controlling a multiple-level inverter bridge as defined in claim 28, said method further comprising:

transforming the flux (d) and torque (q)command signals into signals α and

β

signals via a Park Transform, after inputting the transmitted command signals into the external adapter circuit,

transforming signals α and

β

into three-phase a, b, and c command signals, before generating the twelve-or-more time coordinated signals in the modulator, said modulator of the external adapter circuit generating the twelve-or-more time coordinated signals using the a, b, and c command signals.

31. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the two-level induction motor controller utilizes vector control, said regulator being a flux and torque regulator and said command signals output from the two-level induction motor controller being α

and β

command signals.

32. The method of controlling a multiple-level inverter bridge as defined in claim 31, said method further comprising:

transforming the α and

β

command signals into three-phase a, b, and c command signals, after inputting the transmitted command signals into the external adapter circuit, but before generating the twelve-or-more time coordinated signals in the modulator, said modulator of the external adapter circuit generating the twelve-or-more time coordinated signals using the a, b, and c command signals.

33. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the two-level induction motor controller utilizes vector control, said regulator being a flux and torque regulator and said command signals output from said two-level induction motor controller being three-phase a, b, and c command signals.

34. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the two-level induction motor controller utilizes scalar control, said regulator being a voltage regulator and said command signals output from said two-level induction motor controller being frequency and voltage command signals.

35. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the first interface port is a Controller Area Network serial interface.

36. The method of controlling a multiple-level inverter bridge as defined in claim 25, wherein the modulator of the external adapter circuit is selected from the group consisting of a space-vector modulator, a hysteresis modulator, pulse pattern modulator, and a sine-triangle modulator.