Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction

• US 7,834,880 B2
• Filed: 03/22/2006
• Issued: 11/16/2010
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Remez, Offir, Fogel, Efi
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US11/386,454
• Publication Number:
  US 20060279577A1
• Time in Patent Office: 1,700 Days
• Field of Search: 345/505, 345/519, 345/506, 345/419, 345/520
• US Class Current: 345/519
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.

Claims

1. A silicon chip of a monolithic construction for use in implementing a multi-GPU graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), and a CPU bus, and a display device with a display surface, wherein said computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands, said silicon chip interfacing with said computing system and comprising:

multiple GPU-driven pipeline cores, each said GPU-driven pipeline core having a graphics processing unit (GPU) supporting the parallelization of graphics processing using one or more parallelization modes;

wherein said computing system further supporting multi-pipe drivers allowing said multiple GPU-driven pipeline cores to interact with said graphics libraries;

a compositing unit for compositing images from partial frame buffers of according to a current parallelization mode,

a routing center, operably connected to said CPU bus, for receiving a stream of graphics commands and data from said CPU, and distributing said graphics commands and data among said multiple GPU-driven pipeline cores, and collecting rendered results in the form of partial frame buffers from said multiple GPU-driven pipeline cores, and providing said partial frame buffers to said compositing unit for composition of images, for display on said display surface;

a control unit for controlling the configuring and functioning of said multi-GPU graphics processing and display subsystem according to the current parallelization mode in operation, wherein said stream of graphics commands and data is distributed among said GPU-driven pipeline cores under the control of said control unit and depending on the current parallelization mode;

a processing element (PE), with memory, for processing data within said silicon chip;

a profiling functions unit for delivering benchmarking data to said multi-pipe drivers,

wherein said benchmarking data includes data selected from the group consisting of memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each GPU-driven pipeline core, load balance among said GPU-driven pipelines cores, volumes of transferred data, textures count, and depth complexity; and

a display interface, for displaying composited images on said display surface.

2. The silicon chip of claim 1, wherein said control unit and said current parallelization mode determines how said graphics commands and data are distributed to said GPU-driven pipeline cores.

3. The silicon chip of claim 1, wherein said multi-pipe drivers comprise:

a GPU drivers unit for performing the functions of a generic GPU driver associated with interaction with said operating system and said graphics libraries; and

a distributed graphic functions control module for performing functions associated with different parallelization modes according to a parallelization policy management.

4. The silicon chip of claim 3, wherein said multi-pipe drivers further comprise:

a state monitoring driver module for continuous analysis of all incoming commands, including state commands, transferring certain state commands and some of the data of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven pipeline cores.

5. The silicon chip of claim 4, wherein said multi-pipe drivers further comprise:

an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said computing system identifying problem areas within said multi-GPU graphics processing and display subsystem which are likely to cause data bottlenecks, wherein said application profiling and analysis driver module uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, and (ii) the registers of said control unit, and graphic API commands; and

a parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by said control unit.

6. The silicon chip of claim 1, wherein said memory associated with said processing element comprises cache memory, for serving said processing element and for caching graphics data common to said GPU-driven pipeline cores.

7. The silicon chip of claim 1, wherein said graphics data is selected from the group consisting of textures and vertex objects.

8. The silicon chip of claim 1, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

9. The silicon chip of claim 1, wherein the number of said GPU-driven pipeline cores has no architectural limit.

10. The silicon chip of claim 1, wherein said one or more parallelization modes are selected from the group consisting of an object division mode, an image division mode and a time division mode.

11. The silicon chip of claim 1, wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

12. The silicon chip of claim 1, in combination with said multi-GPU graphics processing and display subsystem.

13. The silicon chip of claim 1, wherein said computing system includes a motherboard on which said CPU is mounted, wherein a graphics card is connected to said motherboard, and wherein said silicon chip is mounted on said motherboard.

14. The silicon chip of claim 13, in combination with said graphics card.

15. The silicon chip of claim 1, wherein said computing system includes a motherboard on which said CPU is mounted, and wherein and said silicon chip is also mounted on said motherboard with said CPU.