Methods and arrangements for enhancing power management systems in integrated circuits

• US 7,835,212 B2
• Filed: 04/09/2008
• Issued: 11/16/2010
• Est. Priority Date: 02/13/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuang, Jente B., Ngo, Hung Cai
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US12/099,913
• Publication Number:
  US 20090016141A1
• Time in Patent Office: 951 Days
• Field of Search: 365/226, 365/227, 365/228, 365/229, 365/233.1, 365/233.11
• US Class Current: 365/226
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

Claims

1. A circuit comprising:

a first group of functionally distinct integrated circuit components configured to be operable during a first time period and to be inactive during at least a portion of a second time period;

a second group of functionally distinct integrated circuit components configured to be inactive during at least a portion of the first time period and operable during the second time period; and

a power cell located in an area of the circuit proximate to the first group and the second group and coupled with the first group and the second group to supply power to the first group and the second group, wherein the power cell is sized based upon power requirements of the first group, wherein the power cell comprises a power switching component adapted to suppress power supplied to the first group of functionally distinct integrated circuit component when the at least a portion of the second time period occurs and to suppress power supplied to the second group of functionally distinct integrated circuit components when the at least a portion of the first time period occurs.

2. The circuit of claim 1, further comprising a power control component coupled with the power cell, wherein the first group and the second group have operational overlap and the power cell is adapted to power the first group and the second group via the power control component by controlling the power switching component to supply power to the first group of functionally distinct integrated circuit components and the second group of functionally distinct integrated circuit components in a staggered fashion.

3. The circuit of claim 1, wherein the first group of functionally distinct integrated circuit component comprises at least one static random access memory (SRAM) cell and the second group of functionally distinct integrated circuit component comprises at least one SRAM cell.

4. The circuit of claim 1, wherein the first group of functionally distinct integrated circuit component comprises a first group of register cells and the second group of functionally distinct integrated circuit component comprises a second group of register cells.

5. The circuit of claim 1, wherein the first group of functionally distinct integrated circuit component comprises at least a first cell adapted to receive a signal from a first leg of a signal branching circuit and the second group of functionally distinct integrated circuit components comprises at least a second cell adapted to receive a signal from a second leg of the signal branching circuit.

6. The circuit of claim 1, wherein the first group of functionally distinct integrated circuit components comprises a first portion of a multiplexer and the second group of functionally distinct integrated circuit components comprises a second portion of the multiplexer.

7. A circuit comprising:

a first integrated circuit component;

a second integrated circuit component wherein the first and second integrated circuit components operate at least partially during non-overlapping time periods; and

a power cell located in an area of the circuit proximate to the first integrated circuit and the second integrated circuit and coupled with the first integrated circuit and the second integrated circuit to supply power to the first integrated circuit and the second integrated circuit, wherein the power cell is sized based upon power requirements of the first integrated circuit, wherein the power cell comprises a power switching component having a first power switch to supply power to the first integrated circuit component and a second power switch to supply power to the second integrated circuit component.

8. The circuit of claim 7, further comprising a power control cell coupled with the power switching component to suppress power to the first integrated circuit component via the first power switch while the first integrated circuit component is inactive.

9. The circuit of claim 7, wherein the first integrated circuit component comprises at least one static random access memory (SRAM) cell and the second integrated circuit component comprises at least one SRAM cell.

10. The circuit of claim 7, wherein the first integrated circuit component comprises a first group of register cells and the second integrated circuit component comprises a second group of register cells.

11. The circuit of claim 7, wherein the first integrated circuit component comprises at least a first cell adapted to receive a signal from a first leg of a signal branching circuit and the second integrated circuit component comprises at least a second cell adapted to receive a signal from a second leg of the signal branching circuit.

12. The circuit of claim 7, wherein the first integrated circuit component comprises a signal processing cell and the second integrated circuit component comprises signal processing cell.

13. The circuit of claim 7, further comprising a power control cell coupled with the power cell, the first integrated circuit and the second integrated circuit have operational overlap, wherein the power control cell is adapted to power, via the power cell and the power switching component, the first integrated circuit and the second integrated circuit by controlling the power switching component to supply power to the first integrated circuit and the second integrated circuit in a staggered fashion.