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Output queued switch with a parallel shared memory, and method of operating same

  • US 7,835,334 B2
  • Filed: 08/26/2008
  • Issued: 11/16/2010
  • Est. Priority Date: 11/29/2000
  • Status: Expired due to Fees
First Claim
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1. A network switch, comprising:

  • an input layer including N input layer circuits, each input layer circuit including an input layer circuit input port and N queues corresponding to N output terminals;

    an intermediate layer including N intermediate layer circuits, each intermediate layer circuit including N buffers positioned between N intermediate layer circuit input terminals and N intermediate layer circuit output terminals; and

    an output layer including N output layer circuits, each output layer circuit having N output layer circuit input terminals and an output layer circuit output port, the N output layer circuit input terminals corresponding to individual intermediate layer circuit output terminals of the N intermediate layer circuits;

    wherein the input layer, the intermediate layer, and the output layer are formed on a single semiconductor substrate, the network switch being configurable to enable a first region of the single semiconductor substrate selected from the input layer, the intermediate layer and the output layer, while disabling two regions of the single semiconductor substrate selected from the input layer, the intermediate layer and the output layer.

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