Methods and systems for digitally processing data signals

• US 7,835,387 B2
• Filed: 07/01/2009
• Issued: 11/16/2010
• Est. Priority Date: 07/21/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gopinathan, Venugopal, Agazzi, Oscar
• Primary Examiner(s): Nguyen; Brian D
• Assistant Examiner(s): Nguyen; Toan D
• Application Number:
  US12/496,211
• Publication Number:
  US 20090310665A1
• Time in Patent Office: 503 Days
• Field of Search: 370/290, 370/463, 370/466, 370/467, 370/497, 375/144, 375/229, 375/232, 375/233, 375/260, 375/262, 375/264, 375/265, 375/267, 375/316, 375/340, 375/341, 375/342, 375/347, 375/350, 375/355, 710/69, 398/79, 398/82, 398/140, 398/141, 398/158, 398/202, 398/208
• US Class Current: 370/463
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/697 Arrangements for reducing noise and distortion
• CPC Class Codes: H04B 10/6971 using equalisation
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection

Abstract

Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.

Claims

1. A method for processing a data signal, comprising:

(1) receiving a data signal having a symbol rate;

(2) generating N sampling signals having a frequency that is lower than the symbol rate, the N sampling signals shifted in phase relative to one another, wherein N is an integer greater than one;

(3) controlling N analog-to-digital converter (“

ADC”

) paths with the N sampling signals to sample the data signal at the phases to produce samples;

(4) performing at least one M-path parallel digital process on the samples, wherein M is greater than N; and

(5) generating a digital signal representation of the data signal from the samples.

2. The method according to claim 1, wherein step (4) further comprises equalizing the samples.

3. The method according to claim 2, wherein step (4) further comprises performing one or more of the following types of equalization processes on the samples:

Viterbi equalization;

feed-forward equalization; and

decision feedback equalization.

4. The method according to claim 1, wherein step (4) comprises decoding a convolutional code.

5. The method according to claim 1, wherein step (4) comprises decoding a trellis code.

6. The method according to claim 1, wherein step (4) comprises decoding a block code.

7. The method according to claim 1, wherein M equals 2N.

8. A receiver, comprising:

an analog-to-digital converter (“

ADC”

) array of N ADC paths, wherein N is an integer greater than 1, each ADC path including an ADC path input coupled to a receiver input; and

an M-path digital signal processor coupled to the ADC array, wherein M is greater than N.

9. The receiver according to claim 8, wherein the digital signal processor comprises an equalizer.

10. The receiver according to claim 9, wherein the equalizer comprises one or more of:

a Viterbi equalizer;

a feed-forward equalizer; and

a decision feedback equalizer.

11. The receiver according to claim 8, wherein the digital signal processor comprises a convolutional decoder.

12. The receiver according to claim 8, wherein the digital signal processor comprises a trellis decoder.

13. The receiver according to claim 8, wherein the digital signal processor comprises a block decoder.

14. The receiver according to claim 8, wherein M equals 2N.

15. A receiver, comprising:

means for receiving a data signal having a symbol rate;

means for generating N sampling signals having a frequency that is lower than the symbol rate, the N sampling signals shifted in phase relative to one another, wherein N is an integer greater than one;

means for controlling N analog-to-digital converter (“

ADC”

) paths with the N sampling signals to sample the data signal at the phases to produce samples;

means for performing at least one M-path parallel digital process on the samples, wherein M is greater than N; and

means for generating a digital signal representation of the data signal from the samples.

16. The receiver according to claim 15, wherein the means for performing digital processes on the samples comprise means for equalizing the samples.

17. The receiver according to claim 16 wherein the means for equalizing comprises one or more of:

performing a Viterbi equalization process in the samples;

performing a feed-forward equalization process on the samples; and

performing a decision feedback equalization process on the samples.

18. The receiver according to claim 15, wherein the means for performing the digital processes on the samples comprises means for decoding a convolutional code.

19. The receiver according to claim 15, wherein the means for performing the digital processes on the samples comprises means for decoding a trellis code.

20. The receiver according to claim 15, wherein the means for performing the digital processes on the samples comprises means for decoding a block code.

21. The receiver according to claim 15, wherein M equals 2N.