Specialized processing block for programmable logic device

• US 7,836,117 B1
• Filed: 07/18/2006
• Issued: 11/16/2010
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Nguyen, Triet M., Langhammer, Martin, Streicher, Keone, Azgomi, Orang, Lee, Kwan Yee Martin
• Primary Examiner(s): Malzahn; David H
• Application Number:
  US11/458,361
• Time in Patent Office: 1,582 Days
• Field of Search: None
• US Class Current: 708/603
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/4812 Complex multiplication
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49963 Rounding to nearest G06F7/49957 takes precedence
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/06 Systolic
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block comprising:

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of multipliers, and

circuitry for adding, in one operation, partial products produced by all of said plurality of multipliers; and

circuitry interconnecting said fundamental processing units, said circuitry interconnecting said fundamental processing units comprising circuitry for selectably combining outputs of said plurality of multipliers of each of a plurality of said fundamental processing units for combined input to said circuitry for adding, whereby said circuitry for adding selectably adds, in said one operation, said partial products produced by all of said plurality of multipliers in each of said plurality of said fundamental processing units.

2. The specialized processing block of claim 1 wherein each of said fundamental processing units further comprises circuitry for shifting said partial products prior to adding them.

3. The specialized processing block of claim 1 further comprising loopback circuitry for feeding back an output of said specialized processing block to an input of said specialized processing block.

4. The specialized processing block of claim 3 wherein said loopback circuitry provides an accumulation function.

5. The specialized processing block of claim 3 wherein said loopback circuitry is used to configure said specialized processing block as an adaptive filter.

6. The specialized processing block of claim 3 further comprising input multiplexing circuitry for distributing inputs from a plurality of sources.

7. The specialized processing block of claim 6 wherein said plurality of sources comprises an input to said specialized processing block and an output of said specialized processing block.

8. The specialized processing block of claim 7 wherein said plurality of sources further comprises an input of another said specialized processing block.

9. The specialized processing block of claim 6 wherein said input multiplexing circuitry comprises registers for registering said inputs.

10. The specialized processing block of claim 9 wherein said registers are chained for inputting data seriatim to each said plurality of multipliers.

11. The specialized processing block of claim 1 further comprising an output stage, said output stage including:

for each of at least one fundamental processing unit of said specialized processing block;

a cascade multiplexer for selecting a previous cascade output,

an output cascade adder for adding an output of said at least one fundamental processing unit to said previous cascade output,

an output multiplexer for selecting between said output of said at least one fundamental processing unit and an output of said output cascade adder, and

first and second conductors for conducting said output of said output cascade adder to respective cascade multiplexers associated with subsequent fundamental processing units.

12. The specialized processing block of claim 11 wherein:

said first conductor conducts said output of said output cascade adder to an immediately subsequent fundamental processing unit;

said second conductor conducts said output of said output cascade adder to a cascade multiplexer associated with a fundamental processing unit immediately subsequent to said immediately subsequent fundamental processing unit; and

each said cascade multiplexer selects among (1) zero, (2) output of an immediately previous output cascade adder, and (3) output of an output cascade adder immediately previous to said immediately previous output cascade adder.

13. A programmable logic device comprising the specialized processing block of claim 1.

14. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 13 coupled to the processing circuitry and the memory.

15. A printed circuit board on which is mounted a programmable logic device as defined in claim 13.

16. The printed circuit board defined in claim 15 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

17. The printed circuit board defined in claim 16 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

18. An integrated circuit device comprising the specialized processing block of claim 1.

19. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

an integrated circuit device as defined in claim 18 coupled to the processing circuitry and the memory.

20. A printed circuit board on which is mounted an integrated circuit device as defined in claim 18.

21. The printed circuit board defined in claim 20 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

22. The printed circuit board defined in claim 21 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

23. The specialized processing block of claim 1 wherein said circuitry for selectably combining comprises:

a compressor in one of said fundamental processing units; and

a multiplexer in a respective other one of said fundamental processing units for selectably inputting said partial products produced by said plurality of multipliers in said respective other one of said fundamental processing units into said compressor in said one of said fundamental processing units.