Ethernet virtualization using hardware control flow override

• US 7,836,198 B2
• Filed: 03/20/2008
• Issued: 11/16/2010
• Est. Priority Date: 03/20/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Turner, Jeffrey M., Haynie, Howard M., Cadigan, Michael J. Jr.
• Primary Examiner(s): Jaroenchonwanit; Bunjob
• Application Number:
  US12/052,264
• Publication Number:
  US 20090240346A1
• Time in Patent Office: 971 Days
• Field of Search: 709/233, 709/235
• US Class Current: 709/233
• CPC Class Codes: G05B 19/052 Linking several PLC's
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A method of Ethernet virtualization using hardware control flow override. The method comprises providing, at a first logical entity of a first programmable logic device, control signals used for performing control-flow, selectively routing the control signals to a second programmable logic device that is external to the first programmable logic device, receiving processed control signals from the second programmable logic device, and forwarding the processed control signals to a second logic entity of the first programmable logic device.

Claims

1. A method of Ethernet virtualization using hardware control flow override, the method comprising:

providing, at a first logical entity of a first programmable logic device, a control signal used for performing control-flow;

generating, from the first logical entity of the first programmable logic device, a first output signal;

responsive to the control signal selecting an override mode, performing a through c comprising;

a) routing the first output signal to a second programmable logic device that is external to the first programmable logic device;

b) based on the first output signal, generating, from the second programmable logic device, a second output signal; and

c) forwarding the second output signal to a second logical entity of the first programmable logic device; and

responsive to the control signal not selecting an override mode, forwarding the first output signal to the second logical entity of the first programmable logic device.