Multi-processor system

• US 7,836,233 B2
• Filed: 08/19/2003
• Issued: 11/16/2010
• Est. Priority Date: 03/05/2003
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Watabe, Mitsuru, Yoshimura, Kentaro, Kanekawa, Nobuyasu, Yokoyama, Takanori, Tsunedomi, Kunihiko
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/642,755
• Publication Number:
  US 20040176857A1
• Time in Patent Office: 2,646 Days
• Field of Search: 710/110, 700/3
• US Class Current: 710/110
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G05B 2219/2231 Master slave
• CPC Class Codes: G05B 2219/25178 Serial communication, data, also repeater

Abstract

A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4. The master processor 3 transfers data to and from the slave processor 2 in communication with the slave processor 2 by means of the data communication section 310 through the fast SPI cable 5 in response to a transmission request command sent from the slave processor 2

With this, the processing ability of a multi-processor system can be increased.

Claims

1. A multi-processor system comprising:

a slave processor;

a first transmission path connected to said slave processor;

a master processor connected to said first transmission path through which said master processor starts to communicate with said slave processor; and

a second transmission path which connects said slave processor and said master processor,

wherein the transmission speed of said second transmission path is less than the transmission speed of said first transmission path, and

wherein said slave processor is equipped with a command transmission means for sending a transmission request command which requests either data transmission or data reception to said master processor via said second transmission path; and

said master processor is equipped with a data transmission means for starting data transmission to said slave processor via said first transmission path in response to said transmission request command.

2. A multi-processor system comprising:

a slave processor, which is defined as a slave relative to a master processor, the slave processor having a first single master type bi-directional communication interface unit and a first multi-master type bi-directional communication interface unit,

wherein the transmission speed of said first multi-master type bi-directional communication interface unit is less than the transmission speed of said first single master type bi-directional communication interface unit;

a master processor, which is defined as a master to start communication with said slave, the master processor having a second single master type bi-directional communication interface unit and a second multi-master type bi-directional communication interface unit,

wherein the transmission speed of said second multi-master type bi-directional communication interface unit is less than the transmission speed of said second single master type bi-directional communication interface unit;

a first transmission cable for connecting said first single master type bi-directional communication interface unit and said second single master type bi-directional communication interface unit; and

a second communication cable for connecting said first multi-master type bi-directional communication interface unit and said second multi-master type bi-directional communication interface unit,

wherein said slave processor is equipped with a first command transmission means for transmitting a transmission request command to request said master processor to start transmission of data from said first multi-master type bi-directional communication interface unit to said master processor via said second communication cable, and

wherein said master processor causes said second single master type bi-directional communication interface unit to start communication with said first single master bi-directional communication interface unit in response to said transmission request command, which was received by said second multi-master type bi-directional communication interface unit, and sends said data to said slave processor via said first communication cable.

3. The multi-processor system of claim 2, wherein said first single master type bi-directional communication interface unit and said second single master type bi-directional communication interface unit are SPI (Serial Peripheral Interface) units.

4. The multi-processor system of claim 2, wherein said first multi-master type bi-directional communication interface unit and said second multi-master type bi-directional communication interface unit are either SCI (Serial Communication Interface) units or IEEE1394 interface units.

5. The multi-processor system of claim 2,

wherein said master processor includes a data communication means and an input means,

wherein said input means connects to an input device and receives output data from said input device,

wherein said slave processor includes a program, which processes said output data received from said input device,

wherein said first command transmission means sends a first transmission request command which requests transmission of said output data received from said input device to said master processor via said first multi-master type bi-directional communication interface unit in response to a request from said program, and

wherein said data communication means causes said second single master type bi-directional communication interface unit to start reception of said output data received from said input device in response to said first transmission request command when said second multi-master type bi-directional communication interface unit receives said first transmission request command.

6. The multi-processor system of claim 5,

wherein said master processor is equipped with a storage means which corresponds to said input device and stores a first input page to include said output data received from said input device,

wherein said slave processor is equipped with a storage means which contains a second input page which corresponds to said first input page,

wherein said first command transmission means sends said first transmission request command which contains a specification of said first input page, and

wherein said data communication means causes said second single master type bi-directional communication interface unit to start to receiving data from said first input page and to store said data received from said first input page in said second input page.

7. The multi-processor system of claim 2,

wherein said master processor includes a data communication means and an output means,

wherein said output means connects to an output device and sends input data to said output device,

wherein said slave processor contains a program to calculate said input data,

wherein said first command transmission means transmits a second transmission request command which requests reception of said input data in response to a request from said program to said master processor via said first multi-master type bi-directional communication interface unit, and

wherein said data communication means causes said second single master type bi-directional communication interface unit to start data transmission to said output device in response to said second transmission request command when said second multi-master type bi-directional communication receives said second transmission request command.

8. The multi-processor system of claim 7,

wherein said slave processor has a storage means related to said output device and contains a first output page in which the input data of said output device is stored by said program,

wherein said first command transmission means transmits said second transmission request command which contains a specification of said first output page,

wherein said data communication means causes said second single master type bi-directional communication interface unit to start transmission of said input data which is stored in said first output page indicated by the specification in said second transmission request command, and

wherein said master processor comprises a storage means which contains a second output page corresponding to said first output page and a data communication means which stores, in said second output page, data which said second single master type bi-directional communication interface unit transmitted in response to said second transmission request command.

9. The multi-processor system of claim 2,

wherein said master processor contains a first program,

wherein said slave processor contains a second program which cooperates with said first program, said first command transmission means transmits a first transmission request command which requests to transmit output data of said first program and a second transmission request command which requests to receive output data of said second program in response to a request from said second program to said master processor via said master processor, and

wherein said data communication means causes said second single master type bi-directional communication interface unit to start transmission of output data of said first program to said second multi-master type bi-directional communication interface unit in response to said first transmission request command when said second multi-master type bi-directional communication interface unit receives said first transmission request command and causes said second multi-master type bi-directional communication interface unit to start reception of the output data of said second program to said first single master type bi-directional communication interface unit in response to said second transmission request command when said second multi-master type bi-directional communication interface unit receives said second transmission request command.

10. The multi-processor system of claim 2,

wherein a third communication cable is provided to connect said first multi-master type bi-directional communication interface unit and said second multi-master type bi-directional communication interface unit,

wherein said master processor is equipped with a second command transmission means which transmits a command to said slave processor from said second multi-master type bi-directional communication interface unit via said third communication cable,

wherein this second command transmission means transmits a confirmation message to said slave processor via said second communication cable from said second multi-master type bi-directional communication interface unit when said second multi-master type bi-directional communication interface unit receives said transmission request command via said second communication cable, and

wherein said first command transmission means transmits a confirmation message to said master processor via said third communication cable when said second multi-master type bi-directional communication interface unit receives said transmission command via said third communication cable.

11. The multi-processor system of claim 2, wherein said first multi-master type bi-directional communication interface unit is provided inside or outside of said slave processor and said second multi-master type bi-directional communication interface unit is provided inside or outside of said master processor.