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System and method for optimizing interconnections of memory devices in a multichip module

  • US 7,836,252 B2
  • Filed: 08/29/2002
  • Issued: 11/16/2010
  • Est. Priority Date: 08/29/2002
  • Status: Active Grant
First Claim
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1. A plurality of memory modules coupled to a controller, each memory module comprising;

  • a substrate having an outer perimeter;

    a memory hub on the substrate, each memory hub for each respective memory module coupled to the controller by a respective memory link, each memory hub operable to receive memory signals from and apply memory signals to its respective memory link, each memory hub being directly coupled to a respective memory hub of another memory module by a hub communication link, each hub communication link operable to transmit memory signals between its two respectively coupled memory hubs; and

    a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and electrically coupled directly to the memory hub.

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