System and method for optimizing interconnections of memory devices in a multichip module
First Claim
1. A plurality of memory modules coupled to a controller, each memory module comprising;
- a substrate having an outer perimeter;
a memory hub on the substrate, each memory hub for each respective memory module coupled to the controller by a respective memory link, each memory hub operable to receive memory signals from and apply memory signals to its respective memory link, each memory hub being directly coupled to a respective memory hub of another memory module by a hub communication link, each hub communication link operable to transmit memory signals between its two respectively coupled memory hubs; and
a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and electrically coupled directly to the memory hub.
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Abstract
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.
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Citations
34 Claims
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1. A plurality of memory modules coupled to a controller, each memory module comprising;
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a substrate having an outer perimeter; a memory hub on the substrate, each memory hub for each respective memory module coupled to the controller by a respective memory link, each memory hub operable to receive memory signals from and apply memory signals to its respective memory link, each memory hub being directly coupled to a respective memory hub of another memory module by a hub communication link, each hub communication link operable to transmit memory signals between its two respectively coupled memory hubs; and a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and electrically coupled directly to the memory hub. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer system, comprising:
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a data input device; a data output device; a processor coupled to the data input and data output devices; a controller electrically coupled to the processor, the controller being operable to receive and transmit memory signals on a plurality of memory links; and a plurality of memory modules, each memory module comprising; a substrate; a memory hub coupled to a respective one of the memory links, each memory hub having electrical output ports for sending and receiving electrical signals, each memory hub being operable to translate received electrical signals to corresponding memory signals to be applied to its respective memory link and translate memory signals into corresponding electrical signals to be applied at the output ports, each memory hub directly coupled to a respective memory hub of another memory module by a hub communication link, each hub communication link operable to transmit memory signals between its two respectively coupled memory hubs; and a plurality of memory devices arranged on the substrate, with all of the memory devices arranged on the substrate located substantially equidistant from the memory hub and electrically coupled directly to a respective output port of the memory hub to receive command, address and data signals from the memory hub and to provide data signals to the memory hub. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification