Method and apparatus for supporting address translation in a virtual machine environment

• US 7,836,275 B2
• Filed: 05/22/2008
• Issued: 11/16/2010
• Est. Priority Date: 01/28/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Anderson, Andrew V., Kägi, Alain
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Bertram; Ryan
• Application Number:
  US12/154,627
• Publication Number:
  US 20090006805A1
• Time in Patent Office: 908 Days
• Field of Search: 711/205, 711/6, 711/206
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure.

Claims

1. A method comprising:

creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and

deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active directory lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed.

2. The method of claim 1 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and

the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs.

3. The method of claim 1 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and

the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list.

4. The method of claim 2 further comprising:

tracking pages used by the guest operating system in forming the guest PT hierarchy; and

tracking mappings to any Dynamic Random Access Memory (DRAM) backed page frame.

5. The method of claim 1 further comprising:

identifying one or more large-size pages in the guest PT hierarchy; and

creating a PT table in the shadow PT hierarchy for each of the one or more large-size pages.

6. The method of claim 1 further comprising:

detecting a change in a structure of the guest PT hierarchy; and

modifying the metadata to reflect the change.

7. The method of claim 1 wherein:

content of the shadow PT hierarchy is used by a processor to cache address translations in the TLB.

8. An apparatus comprising:

a memory to store instructions;

a processor, coupled to the memory; and

an address translator, executed from the memory by the processor to;

create a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and

derive metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active directory lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed.

9. The apparatus of claim 8 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and

the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs.

10. The apparatus of claim 8 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and

the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list.

11. The apparatus of claim 9 wherein the address translator is further executed from the memory by the processor to:

track pages used by the guest operating system in forming the guest PT hierarchy; and

track mappings to any Dynamic Random Access Memory (DRAM) backed page frame.

12. The apparatus of claim 8 wherein the address translator is further executed from the memory by the processor to:

identify one or more large-size pages in the guest PT hierarchy; and

create a PT table in the shadow PT hierarchy for each of the one or more large-size pages.

13. The apparatus of claim 8 wherein the address translator is further executed from the memory by the processor to:

detect a change in a structure of the guest PT hierarchy; and

modify the metadata to reflect the change.

14. The apparatus of claim 8 wherein:

content of the shadow PT hierarchy is used by the processor to cache address translations in the TLB.

15. A non-transient computer readable storage medium including instructions that, when executed by a processing system, cause the processing system to perform a method comprising:

creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and

deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active director,,/lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed.

16. The computer readable storage medium of claim 15 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and

the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs.

17. The computer readable storage medium of claim 15 wherein:

the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and

the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list.

18. The computer readable storage medium of claim 16, wherein the method further comprises:

tracking pages used by the guest operating system in forming the guest PT hierarchy; and

tracking mappings to any Dynamic Random Access Memory (DRAM) backed page frame.

19. The computer readable storage medium of claim 15, wherein the method further comprises:

identifying one or more large-size pages in the guest PT hierarchy; and

creating a PT table in the shadow PT hierarchy for each of the one or more large-size pages.

20. The computer readable storage medium of claim 15, wherein the method further comprises:

detecting a change in a structure of the guest PT hierarchy; and

modifying the metadata to reflect the change.

21. The computer readable storage medium of claim 15 wherein:

content of the shadow PT hierarchy is used by a processor to cache address translations in the TLB.