Implementation of variable length instruction encoding using alias addressing

• US 7,836,285 B2
• Filed: 08/08/2007
• Issued: 11/16/2010
• Est. Priority Date: 08/08/2007
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Giri, Abhijit, Nadig, Rajiv
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/890,907
• Publication Number:
  US 20090043990A1
• Time in Patent Office: 1,196 Days
• Field of Search: None
• US Class Current: 712/229
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.

Claims

1. A method for operating a digital processor by accessing a current instruction, the method comprising:

determining if a virtual address associated with the current instruction belongs to first or second alias space wherein;

a first operating mode is associated with the first alias space and a second operating mode is associated with the second alias space; and

at least one virtual address in the first alias space and at least one virtual address in the second alias space correspond to a single physical-memory address; and

setting the processor in the first or second operating mode according to alias space to which the virtual address associated with the current instruction belongs.

2. A method as defined in claim 1, wherein instructions having virtual addresses in the first alias space have a first instruction length and instructions having virtual addresses in the second alias space have a plurality of instruction lengths.

3. A method as defined in claim 2, wherein one instruction length in the plurality of instruction lengths is the first instruction length.

4. A method as defined in claim 3, further comprising determining a current instruction length in the second mode and aligning a next instruction based on a current instruction length.

5. A method as defined in claim 4, wherein aligning instructions comprises shifting instructions in an instruction alignment buffer in response to the current instruction length.

6. A method as defined in claim 2, wherein accessing an instructions comprises accessing a number of bits corresponding to a longest instruction length on each clock cycle.

7. A method as defined in claim 2, wherein the plurality of instruction lengths comprises second and third instruction lengths.

8. A method as defined in claim 7, wherein the first instruction length is greater than the second and third instruction lengths.

9. A method as defined in claim 7, wherein accessing instructions having associated virtual addresses in the second alias space comprises accessing instructions of mixed instruction lengths in consecutive locations of a physical memory.

10. A method as defined in claim 7, wherein the first instruction length is 48 bits, the second instruction length is 32 bits and the third instruction length is 16 bits.

11. A method as defined in claim 1, wherein the first alias space is a normal word address space and the second alias space is a short word address space.

12. A method as defined in claim 1, wherein the first alias space is a first virtual page of a virtual address space and the second alias space is a second virtual page of the virtual address space.

13. The method of claim 1, wherein the virtual address associated with the current instruction is the virtual address of the current instruction.

14. The method of claim 1, wherein the current instruction is a branch instruction, and the virtual address associated with the current instruction is the virtual address of the target instruction associated with the current instruction.

15. Digital processor apparatus to execute instructions, the apparatus comprising:

a program sequencer configured to generate virtual instruction addresses and to automatically switch between a first operating mode and a second operating mode in response to a transition in virtual instruction addresses between a first alias space and a second alias space, wherein at least one virtual address in the first alias space and at least one virtual address in the second alias space correspond to a single physical-memory address.

16. Digital processor apparatus as defined in claim 15, wherein the program sequencer is configured to switch from the first mode to the second mode in response to a transition in virtual instruction addresses from the first alias space to the second alias space and is configured to switch from the second mode to the first mode in response to a transition in virtual instruction addresses from the second alias space to the first alias space.

17. Digital processor apparatus as defined in claim 15, wherein the program sequencer is configured to access instructions of a first instruction length in the first alias space and to access instructions of a plurality of instruction lengths in the second alias address space.

18. Digital processor apparatus as defined in claim 17, wherein one instruction length in the plurality of instruction lengths is the first instruction length.

19. Digital processor apparatus as defined in claim 17, wherein the plurality of instruction lengths comprises second and third instruction lengths.

20. Digital processor apparatus as defined in claim 19, wherein the first instruction length is greater than the second and third instruction lengths.

21. Digital processor apparatus as defined in claim 19, wherein the first instruction length is 48 bits, the second instruction length is 32 bits and the third instruction length is 16 bits.

22. Digital processor apparatus as defined in claim 17, wherein the program sequencer is configured to fetch a number of bits corresponding to a maximum length instruction on each clock cycle.

23. Digital processor apparatus as defined in claim 17, further comprising a decoder to determine a current instruction length in the second mode and an instruction alignment buffer to align a next instruction in response to the current instruction length.

24. Digital processor apparatus as defined in claim 23, wherein the instruction alignment buffer is configured to shift instructions in response to the current instruction length.

25. Digital processor apparatus as defined in claim 15, wherein the program sequencer is configured to detect a virtual address of a target instruction of a branch instruction and to switch between the first mode and the second mode in response to detecting that the virtual address of the target instruction represents a transition between the first alias space and the second alias space.

26. Digital processor apparatus as defined in claim 15, wherein the first alias space is a normal word address space and the second alias space is a short word address space.

27. Digital processor apparatus as defined in claim 15, wherein the first alias space is a first virtual page of a virtual address space and the second alias space is a second virtual page of the virtual address space.