System and method for protecting the contents of memory during error conditions

• US 7,836,331 B1
• Filed: 05/15/2007
• Issued: 11/16/2010
• Est. Priority Date: 05/15/2007
• Status: Active Grant

• Current Assignee: Network Appliance Incorporated (NetApp, Inc.)
• Original Assignee: NetApp, Inc.
• Inventors: Totolos, George Jr.
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US11/748,972
• Time in Patent Office: 1,281 Days
• Field of Search: 714/5
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A system and method protects the contents of memory during error conditions. An illustrative storage system includes a complex programmable logic device (CPLD) that interfaces with a memory controller and a basic input output system (BIOS) for ensuring that the system memory is maintained in a self refresh state in the event of an error condition. The memory controller is configured to, in response to receiving a signal from the CPLD, cause the memory to enter the self refresh state where it is maintained by a battery subsystem (or alternate power sources). Accordingly, data contained within the memory may be replayed to persistent storage upon correction of the error condition via, for example, a system re-initialization.

Claims

1. A system to preserve memory, the system comprising:

a memory operatively interconnected with a memory controller and a logic device, the logic device further coupled to a battery subsystem configured to enable refresh operations to the memory, the logic device further configured to, in response to detecting an error condition, assert a signal to the memory controller causing the memory controller to place the memory in a low-power, self-refresh state, wherein the logic device is further configured to monitor a set of signal lines between the memory controller and the memory to determine whether the memory is in the low-power, self-refresh state.

2. The system of claim 1 further comprising, wherein the logic device is a customizable programmable logic device (CPLD), a basic input output system (BIOS) interconnected with the CPLD.

3. The system of claim 2 further comprising a valid signal between the BIOS and the logic device, wherein assertion of the valid signal indicates that the contents of the memory are protected.

4. The system of claim 3 wherein, in response to detecting that the valid signal is asserted, the BIOS is configured to restore a set of registers associated with the memory.

5. The system of claim 1 further comprising an indicator configured to alert an administrator when the memory is in the low-power, self-refresh state.

6. The system of claim 1 wherein the error condition comprises a loss of main power.

7. The system of claim 1 wherein the error condition comprises assertion of a reset signal.

8. The system of claim 1 wherein the memory comprises one or more dual in line memory modules.

9. The system of claim 1 wherein the logic device comprises a field programmable gate array.

10. The system of claim 1 wherein the memory controller is configured to flush contents of a set of internal buffers to the memory prior to placing the memory in the low-power, self-refresh state.

11. The system of claim 1 wherein only a portion of the memory is placed in the low-power, self-refresh state.

12. The system of claim 1 wherein the set of signal lines comprise a set of clock enable signal lines.

13. The system of claim 1 wherein the error condition comprises a system reset signal being activated.

14. The system of claim 13 wherein the logic device is configured to prevent the reset signal from propagating to the memory controller until the memory is safely in the low-power, self-refresh state.

15. The system of claim 14 wherein the logic device is further configured to, in response to detecting that the memory has been placed in the low-power, self-refresh state, asserting a reset signal to the memory controller.

16. A method for protecting memory of a computer system, comprising:

determining whether a shutdown of the computer system is a result of an error condition or a clean shutdown;

in response to the shutdown being a clean shutdown, flushing data from the memory to persistent storage; and

in response to the shutdown being an error condition, asserting a trigger signal directed to a memory controller, writing, by the memory controller, contents of a set of buffers to the memory, and placing the memory into a self refresh mode.

17. The method of claim 16 wherein the error condition comprises a power loss.

18. The method of claim 16 wherein placing the memory into a self refresh mode further comprises placing only a portion of the memory into the self refresh mode.

19. The method of claim 16 further comprising disallowing, by the memory controller, operations directed to the memory from a processor.

20. A system for protecting memory of a computer system, comprising:

means for determining whether a shutdown of the computer system is a result of an error condition or a clean shutdown;

means for flushing data from the memory to persistent storage in response to the shutdown being a clean shutdown; and

means for asserting a trigger signal directed to a memory controller, writing contents of a set of buffers to the memory, and placing the memory into a self refresh mode in response to the shutdown being an error condition.

21. The system of claim 20 wherein the means for placing the memory into a self refresh mode further comprises means for placing only a portion of the memory into the self refresh mode.

22. A computer readable medium containing executable program instructed executed by a processor, comprising:

program instructions that determine whether a shutdown of a computer system is a result of an error condition or a clean shutdown;

program instructions that flush data from memory to persistent storage in response to the shutdown being a clean shutdown; and

program instructions that assert a trigger signal directed to a memory controller, write contents of a set of buffers of the memory controller to the memory, and place the memory into a self refresh mode in response to the shutdown being an error condition.

23. The computer readable medium of claim 22 wherein the error condition comprises a power loss.

24. The computer readable medium of claim 22 wherein the program instructions that place the memory into a self refresh mode further comprises program instructions that place only a portion of the memory into the self refresh mode.

25. A system to preserve memory contents, the system comprising:

a processor to determine if a shutdown of the system is a result of an error condition or a clean shutdown;

a volatile memory operatively interconnected with a memory controller and a logic device, the logic device further coupled to a battery subsystem, the memory configured to flush data stored in the memory to persistent storage in response to the shutdown of the system being a clean shutdown; and

the logic device configured to assert a trigger signal to the memory controller causing the memory controller to place the memory into a low-power, self-refresh state in response to the shutdown being an error condition.

26. The system of claim 25 memory controller is further configured to flush contents of a set of internal buffers to the memory prior to placing the memory in the low-power, self-refresh state.

27. The system of claim 25 wherein the memory controller is configured to place the memory into the low-power, self-refresh state without software intervention.

28. The system of claim 25 wherein the memory controller is further configured to hold a set of signal lines in a state to thereby cause the memory to remain in the low-power, self refresh state and to ignore operations directed to the memory until the set of signal lines are cleared.

29. The system of claim 28 wherein the set of signal lines comprises a set of clock enabled signal lines.

30. The system of claim 28 wherein the memory controller holds the set of signal lines in the state by asserting a reset pin of a register operatively interconnected between the memory controller and the memory.

31. The system of claim 25 wherein placing the memory into the low-power, self-refresh state renders the memory non-volatile.

32. A method to preserve memory in a computer system, comprising:

coupling the memory to a memory controller and a logic device, wherein the logic device is coupled to a battery subsystem to enable refresh operations to the memory;

in response to detecting an error condition, asserting a signal from the logic device to the memory controller causing the memory controller to place the memory in a low-power, self-refresh state; and

monitoring, by the logic device, a set of signal lines between the memory controller and the memory to determine whether the memory is in the low-power, self-refresh state.

33. The method of claim 32 wherein the error condition comprises a power loss.

34. The method of claim 32 wherein placing the memory into a self refresh mode further comprises placing only a portion of the memory into the self refresh mode.

35. The method of claim 32 further comprising disallowing, by the memory controller, operations directed to the memory from a processor.

36. A computer readable medium containing executable program instructions executed by a processor, comprising:

program instructions that couple a memory to a memory controller and a logic device, wherein the logic device is coupled to a battery subsystem to enable refresh operations to the memory;

program instructions that assert a signal from the logic device to the memory controller causing the memory controller to place the memory in a low-power, self-refresh state in response to detecting an error condition; and

program instructions that monitor, by the logic device, a set of signal lines between the memory controller and the memory to determine whether the memory is in the low-power, self-refresh state.