System to detect and identify errors in control information, read data and/or write data

• US 7,836,378 B2
• Filed: 02/21/2008
• Issued: 11/16/2010
• Est. Priority Date: 05/18/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Fred, Wang, Yuanlong, Shaeffer, Ian, Hampel, Craig
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US12/035,022
• Publication Number:
  US 20080163007A1
• Time in Patent Office: 999 Days
• Field of Search: 714/763, 714/758, 714/768
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.

Claims

1. A memory device, comprising:

device-resident error management circuitry to generate an error management code for each write transaction;

device-resident error management circuitry to generate an error management code for each read transaction; and

transmission circuitry to output information representing the error management codes for each write transaction and the error management codes for each read transaction to a remote controller for comparison with stored error management codes.

2. The device of claim 1, wherein the device-resident error management circuitry to generate the error management code for each write transaction and the device-resident error management circuitry to generate the error management code for each read transaction are included in common circuitry;

and wherein the common circuitry includes;

circuitry to generate a cycle redundancy checking code (CRC) for each write transaction or read transaction and to store at least one of the CRCs in a device-resident buffer.

3. The device of claim 1, wherein:

the transmission circuitry includes a compression circuitry to compress plural error management codes together representing multiple transactions, to create compressed information; and

the device is to transmit the compressed information to the remote controller for comparison, such that all error detection in write and read transactions involving the device occurs at a remote controller end of transactions notwithstanding whether the transactions are write or read transactions.

4. The device of claim 1, wherein the memory device is an integrated circuit memory device.

5. The device of claim 1, further comprising at least a device-resident circular buffer to store the error management code for each write transaction and the error management code for each read transaction.

6. The device of claim 1, wherein the transmission circuitry includes:

a buffer to store the information representing the error management code for each write transaction and the error management code for each read transaction; and

synchronization logic, implemented as at least one of hardware, firmware or software that recycles buffer storage locations for new transactions, at least for buffer storage locations corresponding to error-free performed transactions.

7. The device of claim 6, wherein the error management code for each write transaction and the error management code for each read transaction each includes at least an error detection code.

8. The device of claim 1, wherein the transmission circuitry includes:

a buffer to store plural error codes; and

synchronization logic, implemented as at least one of hardware, firmware or software that selectively outputs the plural error management codes to the remote controller upon an occurrence of a predetermined event.

9. The device of claim 8, wherein the predetermined event is a read transaction initiated by the remote controller, wherein the device further comprises at least one control bit line, and wherein the synchronization logic outputs the plural error management codes via the at least one control bit line upon receipt of the read transaction.

10. The device of claim 9, wherein the at least one control bit line includes at least one data mask bit line, and wherein the synchronization logic outputs compressed information representing the plural error management codes via the at least one data mask bit line during the read transactions.

11. The device of claim 8, wherein the predetermined event includes a receipt of a predetermined command from the remote controller.

12. The device of claim 8, wherein the device further comprises at least one serial control line and wherein the synchronization logic outputs the plural error management codes to the remote controller via the at least one serial control line.

13. A method of a system, comprising:

generating error management codes for each transaction involving a memory device corresponding to at least plural transaction types;

outputting information representing the error management codes to a controller; and

comparing at the controller the information representing the error management codes with stored error management codes to determine whether each transaction was correctly performed.

14. The method of claim 13, wherein the plural transaction types include at least read transactions and write transactions.

15. The method of claim 13, wherein the controller is one of a system central processing unit (CPU) or a dedicated memory subsystem controller, and wherein the memory device is an integrated circuit memory device.

16. The method of claim 13, further comprising retrying a transaction that is determined to have been incorrectly performed.

17. The method of claim 13, wherein:

the method further comprises storing the error management codes in the memory device to selectively output to the controller; and

outputting includes triggering outputting through controller-issuance of a command to the memory device.

18. The method of claim 13, further comprising generating the information representing the error management codes by compressing together the error management codes together, to collectively represent multiple transactions involving the memory device.

19. The method of claim 13, wherein the at least plural transaction types includes at least one type of control transaction, and further comprising retrying each memory transaction following a determination of an error in a transaction involving the at least one type of control transaction.

20. The method of claim 19, wherein:

the method further comprises distinguishing errors representing read and write transactions from errors representing the at least one type of control transaction, and retrying transactions when the error involves a read transaction or a write transaction and not any type of control transaction.

21. The method of claim 13, wherein the outputting information includes compressing together error management codes representing plural recent transactions, the method to compress together error management codes representing multiple transaction types when represented among the plural recent transactions.

22. The method of claim 13, wherein the outputting includes uploading the information representing the error management codes to the controller via one or more data mask lines during a read transaction.

23. The method of claim 13, further comprising synchronizing the memory device and the controller on an intermittent basis, the synchronizing including recycling locations of a memory device storage buffer to permit reuse of the locations for new memory transactions.

24. A method of managing error in a system having memory and a controller, comprising:

generating in the memory, at least one error management code for each transaction that involves either a write or a read operation;

outputting the at least one error management code to the controller; and

comparing the at least one error management code with a stored error management code at the controller to determine whether error has occurred involving the write or read operation.

25. The method of claim 24, wherein the memory is an integrated circuit memory device.

26. The method of claim 24, further comprising in response to error detected by the controller, performing a controller-initiated retry operation.

27. The method of claim 24, wherein outputting the information includes:

generating an error management code within the memory for each write or read operation;

storing the error management codes within the memory;

compressing together plural error management codes to create compressed information;

transmitting the compressed information to the controller; and

using the compressed information for analysis to determine whether error has occurred.

28. The method of claim 27, wherein transmitting includes transmitting the compressed information to the controller upon an occurrence of a predetermined event.

29. The method of claim 24, wherein outputting includes transmitting the information to the controller on a control line not including a bidirectional data bus used for primary transfer of data to be stored in memory.

30. A memory device, comprising:

device-resident error management circuitry to generate an error management code corresponding to at least one of read data or write data;

device-resident error management circuitry to generate an error management code corresponding to a memory address associated with the at least one of read data or write data; and

transmission circuitry to output information representing the error management codes to a controller for comparison with stored error management codes.

31. The device of claim 30, wherein the device-resident error management circuitry to generate the error management code corresponding to at least one of read data or write data and the device-resident error management circuitry to generate the error management code corresponding to a memory address are included in common circuitry;

and wherein the common circuitry includes;

circuitry to generate a cycle redundancy checking code (CRC) for each write transaction or read transaction.

32. The device of claim 30, wherein:

the transmission circuitry includes a compression circuitry to compress plural error management codes together to address information as well as transaction information; and

the device to transmit the compressed information to the controller for comparison, such that all error detection in write and read transactions involving the device occurs at a controller end of transactions notwithstanding whether the transactions are write or read transactions.

33. The device of claim 30, wherein the memory device is an integrated circuit memory device.

34. A dynamic random access memory, including:

an error detection code generator to generate codes for both of (a) at least one of read data or write data, and (b) an address corresponding to the at least one of read data or write data; and

a channel to transmit error detection information representing error detection codes after generation to another device for comparison with stored error codes.

35. A dynamic random access memory according to claim 34, wherein:

the error detection code generator generates codes for each of read data or write data; and

said memory further comprises transmission circuitry to transmit error detection information representing both of (a) a read or write data transaction and (b) associated address information to the other device for comparison.

36. A dynamic random access memory according to claim 35, further comprising a buffer for storing error detection information representing both of (a) and (b) prior to transmission to the other device, such that transmission of error detection codes is delayed relative to the read or write transaction.

37. A dynamic random access memory according to claim 36 wherein the error detection code information includes a compressed CRC code that represents both address information and at least one transaction.

38. A method, comprising:

generating error management codes representing (a) accuracy of each transaction involving a memory device for at least one of a read transaction or a write transaction and (b) accuracy of a memory address affected by the transaction;

outputting the error management codes to a controller; and

comparing at the controller the error management codes with stored codes to determine whether the associated transaction was correctly performed.

39. The method of claim 38, wherein:

generating error management codes includes generating error management codes for each read transaction or write transaction, and the accuracy of an associated memory address; and

wherein outputting error management codes includes outputting the error management codes representing both of the transaction and the associated memory address.

40. The method of claim 39, further comprising retrying a transaction that is determined to have been incorrectly performed.

41. The method of claim 39, wherein the method further comprises storing the error management codes in the memory device for a period of time before selectively outputting the codes to the controller.