Destination indication to aid in posted write buffer loading
First Claim
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1. A volatile memory device formed on an integrated circuit, the memory device comprising:
- a memory array having a first memory array portion and a second memory array portion;
a posted write buffer (PWB) coupled with the memory array, wherein the posted write buffer includes a first PWB element located proximate to the first memory array portion and a second PWB element located proximate to the second memory array portion; and
logic to detect a destination indication associated with received write data, wherein the logic determines whether to store the received write data in the first PWB element or the second PWB element based, at least in part, on the destination indication.
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Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to detect a destination indication associated with received write data. In some embodiments, the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication. Other embodiments are described and claimed.
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Citations
16 Claims
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1. A volatile memory device formed on an integrated circuit, the memory device comprising:
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a memory array having a first memory array portion and a second memory array portion; a posted write buffer (PWB) coupled with the memory array, wherein the posted write buffer includes a first PWB element located proximate to the first memory array portion and a second PWB element located proximate to the second memory array portion; and logic to detect a destination indication associated with received write data, wherein the logic determines whether to store the received write data in the first PWB element or the second PWB element based, at least in part, on the destination indication. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a memory controller; and a memory device formed on an integrated circuit the memory device coupled with the memory controller, the memory device including a memory array having a first memory array portion and a second memory array portion; a posted write buffer (PWB) coupled with the memory array, wherein the posted write buffer includes a first PWB element located proximate to the first memory array portion and a second PWB element located proximate to the second memory array portion; and logic to detect a destination indication associated with received write data, wherein the logic determines whether to store the received write data in the first PWB element or the second PWB element based, at least in part, on the destination indication. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification