Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

• US 7,836,450 B2
• Filed: 01/11/2006
• Issued: 11/16/2010
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Primary Examiner(s): An, Meng-Ai
• Assistant Examiner(s): Kawsar, Abdullah Al
• Application Number:
  US11/330,915
• Publication Number:
  US 20060190945A1
• Time in Patent Office: 1,770 Days
• Field of Search: None
• US Class Current: 718/100
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.

Claims

1. A multiprocessing system, comprising:

a multithreading microprocessor, comprising;

a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether said TC is exempt from servicing interrupt requests to an exception domain for said plurality of TCs; and

a virtual processing element (VPE), comprising said exception domain, configured to receive said interrupt requests, wherein said interrupt requests are non-specific to said plurality of TCs, wherein said VPE is configured to select a non-exempt one of said plurality of TCs to service each of said interrupt requests, said VPE further comprising a second control indicator for controlling whether said VPE is enabled to select one of said plurality of TCs to service said interrupt requests; and

a multiprocessor operating system (OS), configured to initially set said second control indicator to enable said VPE to service said interrupts, and further configured to schedule execution of threads on said plurality of TCs, wherein each of said threads is configured to individually disable itself from servicing said interrupts by setting said first control indicator, rather than by clearing said second control indicator, and individually enable itself to service said interrupts by clearing said first control indicator, rather than by setting said second control indicator.

2. The system as recited in claim 1, wherein said first control indicator comprises a MIPS Multithreading Application Specific Extension (MT ASE) interrupt exempt (IXMT) bit in a TCStatus register.

3. The system as recited in claim 1, wherein said second control indicator comprises a MIPS Privileged Resource Architecture (PRA) interrupt enable (IE) bit in a Coprocessor 0 Status register of said VPE.

4. A method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs) each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests, the method comprising:

initially setting the second control indicator to enable the VPE to service the interrupts;

scheduling execution of threads on the plurality of TCs; and

each of the threads, individually disabling itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator, and individually enabling itself to service the interrupts by clearing the first control indicator, rather than by setting the second control indicator.

5. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium, having computer readable program code embodied in said medium, for causing a method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs) each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests, said computer readable program code comprising;

first program code for providing a step of initially setting the second control indicator to enable the VPE to service the interrupts;

second program code for providing a step of scheduling execution of threads on the plurality of TCs; and

third program code for providing a step of each of the threads, individually disabling itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator, and individually enabling itself to service the interrupts by clearing the first control indicator, rather than by setting the second control indicator.

6. A method for providing operating system software for running on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs) each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests, the method providing computer-readable program code stored in a computer usable medium describing the operating system software, the program code comprising:

first program code for providing a step of initially setting the second control indicator to enable the VPE to service the interrupts;

second program code for providing a step of scheduling execution of threads on the plurality of TCs; and

third program code for providing a step of each of the threads, individually disabling itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator, and individually enabling itself to service the interrupts by clearing the first control indicator, rather than by setting the second control indicator.