Gate dielectric first replacement gate processes and integrated circuits therefrom

• US 7,838,356 B2
• Filed: 12/31/2008
• Issued: 11/23/2010
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yu, Shaofeng, Mehrad, Freidoon, Kirkpatrick, Brian K.
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US12/347,197
• Publication Number:
  US 20100164006A1
• Time in Patent Office: 692 Days
• Field of Search: 438/203, 438/225, 438/262, 438/282, 438/292
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

Claims

1. A method comprising:

forming a gate dielectric layer on PMOS regions for PMOS devices and NMOS regions for NMOS devices;

forming an original gate electrode layer on the gate dielectric layer in both the PMOS regions and the NMOS regions, wherein the original gate electrode layer is doped with material of a first conductivity type;

applying a gate masking layer on the gate electrode layer;

etching to pattern the original gate electrode layer to simultaneously form original gate electrodes for PMOS devices and NMOS devices;

forming source/drain regions for the PMOS devices and the NMOS devices;

removing the original gate electrodes for at least one of the PMOS devices and the NMOS devices to form trenches using an wet etch process with a wet etch solution, wherein the wet etch solution is more reactive with layers doped with the first conductivity type than layers doped with a second conductivity type, and wherein the wet etch solution is generally nonreactive with the gate dielectric layer, and wherein at least a portion of the gate dielectric layer is preserved; and

forming replacement gates in the trenches.

2. The method of claim 1, wherein the original gate electrodes for both the PMOS devices and the NMOS devices are removed during the removing step.

3. The method of claim 1, wherein the original gate electrode layer comprises polysilicon that is doped with an N-type material to a level of at least 1×

10¹⁷ cm<sup>−

3</sup>.

4. The method of claim 3, wherein the step of forming the original gate electrode layer further comprises implanting the N-type material with a maskless blanket implant.

5. The method of claim 1, wherein the original gate electrode layer comprises polysilicon and the forming an original gate electrode layer comprises in-situ n-type doping to a level of at least 1×

10¹⁷ cm<sup>−

3</sup>.

6. The method of claim 1, wherein the the wet etch solution further comprising an aqueous solution having at least one non-alkali metal hydroxide.

7. The method of claim 6, wherein the non-alkali metal hydroxide comprises NH₄OH.

8. The method of claim 7, wherein the wet etch solution comprises 1:

20 to 1;

200 of the NH₄OH in deionized water.

9. The method of claim 1, wherein the original gate electrode layer further comprises a silicide and, wherein the wet etch solution further comprising a base and an oxidizer.

10. The method of claim 1, wherein the method further comprises:

depositing at least one pre-planarization dielectric layer, following the step of forming source/drain regions; and

chemical mechanical polishing to planarize and expose the original gate electrode layer before the removing step.

11. The method of claim 1, wherein the gate masking layer further comprises a hardmask inorganic anti-reflective coating layer.

12. The method of claim 1, wherein the gate dielectric layer comprises a high-k dielectric material having a k-value that is greater than 10.

13. The method of claim 12, wherein the high-k dielectric material comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

14. The method of claim 1, wherein the replacement gates further comprise hafnium, zirconium, tungsten, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, or an electrically conductive metal oxide.

15. A method comprising:

providing a substrate having a semiconductor surface, the semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices;

forming a gate dielectric layer on the PMOS regions and the NMOS regions, wherein the gate dielectric layer comprises a high-k dielectric material having a k-value that is greater than 10;

forming an original polysilicon comprising gate electrode layer on the gate dielectric;

doping the original polysilicon comprising gate electrode layer in both the PMOS regions and the NMOS regions n-type to a doping level of at least 1×

10¹⁸ cm <sup>−

3</sup>;

applying a gate masking layer on the original polysilicon comprising gate electrode layer;

etching to pattern the original polysilicon comprising gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and the NMOS devices;

forming source/drain regions for the PMOS devices and the NMOS devices;

depositing at least one pre-planarization dielectric layer;

chemical mechanical polishing to planarize and expose the original gate electrodes;

removing the original gate electrodes for the PMOS devices and the NMOS devices to form trenches using a wet etch solution comprising at least one non-alkali hydroxide solution, wherein at least a portion of the high-k gate dielectric layer is preserved; and

forming replacement gates in the trenches.

16. The method of claim 15, wherein the hydroxide comprising solution comprises 1:

20 to 1;

200 of NH₄OH in deionized water.

17. A method comprising:

forming a gate dielectric layer on a substrate;

forming an original gate electrode layer on the gate dielectric layer, wherein the original gate dielectric layer is doped with an N-type material;

patterning the original gate electrode layer to form gate electrodes for a plurality of NMOS transistors and a plurality of PMOS transistors;

forming source/drain regions for the PMOS and NMOS transistors;

forming an etch stop layer over the NMOS and PMOS transistors;

forming a photoresist layer over the at least one of the NMOS transistors and the PMOS transistors so that a portion of the etch stop layer is exposed;

removing the exposed etch stop layer;

removing exposed original gate electrodes with a wet etch solution to form trenches, wherein the wet etch solution is more reactive with layers doped with N-type materials than layers doped with P-type materials, and wherein the wet etch solution is generally nonreactive with the gate dielectric layer; and

forming replacement gates electrodes in the trenches.

18. The method of claim 17, wherein the wet etch solution further comprises aqueous NH₄OH.

19. The method of claim 18, wherein the concentration of NH₄OH in deionized water is between about 1:

20 and about 1;

200.

20. The method of claim 19, wherein the original gate electrode layer is a polysilicon layer doped with the N-type material.

21. The method of claim 19, wherein the step of forming the original gate electrode layer further comprises forming an in-situ doped polysilicon layer as the original gate electrode layer.

22. The method of claim 19, wherein the step of forming the original gate electrode layer further comprises:

forming a polysilicon layer on the gate dielectric layer;

implanting the polysilicon layer with the N-type material; and

annealing the polysilicon layer to form the original gate electrode layer.

23. The method of claim 17, wherein the step of forming the replacement gate electrodes in the trenches further comprises:

forming a replacement gate metal layer over the NMOS and PMOS transistors;

patterning the replacement gate metal layer; and

forming a gate electrode filler layer over the NMOS and PMOS transistors after the step of patterning the replacement gate metal layer.

24. The method of claim 23, wherein the step of forming the replacement gate electrodes in the trenches further comprises forming a barrier layer over the NMOS and PMOS transistors prior to the step of forming the gate electrode filler layer.