Electronic device including trenches and discontinuous storage elements

• US 7,838,922 B2
• Filed: 01/24/2007
• Issued: 11/23/2010
• Est. Priority Date: 01/24/2007
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong Min, Li, Chi-Nan
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): Quinto; Kevin
• Application Number:
  US11/626,753
• Publication Number:
  US 20080173921A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257314-334, 257/213, 257/288, 257E29126-E29129, 257E293-E29309
• US Class Current: 257/319
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate outside of the trench, and a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench. The electronic device can also include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench. Processes of forming and using the electronic device are also described.

Claims

1. An electronic device comprising:

a substrate having a primary surface and including a trench having a bottom and a first wall;

a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, wherein the first gate electrode includes a portion that extends to an elevation higher than an elevation of the primary surface of the substrate;

a second gate electrode overlying the substrate outside of the trench;

a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench; and

discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench, and wherein the first set of the discontinuous storage elements include silicon nanocrystals or metal nanoclusters.

2. The electronic device of claim 1, further comprising a first source/drain region and a second source/drain region, wherein:

the first source/drain region lies within the substrate below the bottom of the trench and adjacent to the third gate electrode; and

the second source/drain region lies within the substrate outside of the trench and adjacent to the second gate electrode.

3. The electronic device of claim 2, wherein the first gate electrode, the second gate electrode, the third gate electrode, the first set of discontinuous storage elements, the first source/drain region, and the second source/drain region are parts of a first memory cell.

4. The electronic device of claim 3, wherein the first gate electrode lies between the first wall of the trench and the third gate electrode.

5. The electronic device of claim 4, wherein the first set of discontinuous storage elements lie between the first wall of the trench and the first gate electrode.

6. The electronic device of claim 3, further comprising:

a fourth gate electrode within the trench and adjacent to a second wall of the trench and overlying the bottom of the trench;

a fifth gate electrode overlying the substrate outside of the trench;

a sixth gate electrode within the trench and adjacent to the fourth gate electrode and overlying the bottom of the trench; and

a third source/drain region lying within the substrate outside of the trench and adjacent to the fifth gate electrode,

wherein;

the discontinuous storage elements includes a second set of discontinuous storage elements, wherein the second set of the discontinuous storage elements lies adjacent to the second wall of the trench; and

the fourth gate electrode, the fifth gate electrode, the sixth gate electrode, the second set of discontinuous storage elements, the second source/drain region, and the third source/drain region are parts of a second memory cell.

7. The electronic device of claim 6, wherein each of the first memory cell and the second memory cell is operable to store 2 bits of data.

8. The electronic device of claim 2, wherein:

the first set of discontinuous storage elements lies between the first gate electrode and the first wall;

no discontinuous storage element lies between the second gate electrode and the primary surface of the substrate;

the third gate electrode has a base substantially parallel to the bottom of the trench; and

no discontinuous storage element lies between the base of the third gate electrode and the bottom of the trench.

9. The electronic device of claim 1, wherein each of the first gate electrode, the second gate electrode, and third gate electrode has an arc-shaped edge.

10. The electronic device of claim 9, wherein the second gate electrode comprises a base, and the first set of the discontinuous storage elements underlies the base of the second gate electrode.

11. An electronic device comprising:

a substrate having primary surface and including a trench having a bottom and a first wall;

a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, wherein the first gate electrode includes a portion that extends to an elevation higher than an elevation of the primary surface of the substrate;

a second gate electrode overlying the substrate outside of the trench;

a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench; and

discontinuous storage elements including a first set and a second set of discontinuous storage elements, wherein;

within a first memory cell, the discontinuous storage elements include individual discontinuous storage elements that are substantially physically separated from each other;

the first set of discontinuous storage elements lies between the second gate electrode and the substrate; and

the second set of discontinuous storage elements lies between the third gate electrode and the bottom of the trench.

12. The electronic device of claim 11, further comprising a first source/drain region and a second source/drain region, wherein:

the first source/drain region lies within the substrate below the bottom of the trench and adjacent to the third gate electrode; and

the second source/drain region lies within the substrate outside of the trench and adjacent to the second gate electrode.

13. The electronic device of claim 12, wherein the first gate electrode, the second gate electrode, the third gate electrode, the first and second sets of discontinuous storage elements, the first source/drain region, and the second source/drain region are parts of the first memory cell.

14. The electronic device of claim 13, further comprising a second memory cell, wherein each of the first memory cell and the second memory cell is operable to store 2 bits of data.

15. The electronic device of claim 13, further comprising:

a fourth gate electrode within the trench and adjacent to a second wall of the trench and overlying the bottom of the trench;

a fifth gate electrode overlying the substrate outside of the trench;

a sixth gate electrode within the trench and adjacent to the fourth gate electrode and overlying the bottom of the trench; and

a third source/drain region lying within the substrate outside of the trench and adjacent to the fifth gate electrode,

wherein;

the discontinuous storage elements includes a third set of discontinuous storage elements, wherein the third set of the discontinuous storage elements lies adjacent to the second wall of the trench; and

the fourth gate electrode, the fifth gate electrode, the sixth gate electrode, the third set of discontinuous storage elements, the second source/drain region, and the third source/drain region are parts of a second memory cell.

16. The electronic device of claim 13, wherein the third gate electrode comprises a base, and the first set of the discontinuous storage elements also underlies the base of the third gate electrode.

17. The electronic device of claim 13, wherein the first gate electrode, the second gate electrode, the third gate electrode, the first and second sets of discontinuous storage elements are parts of a memory cell operable to store 4 bits of data.

18. The electronic device of claim 13, wherein the first gate electrode lies between the first wall of the trench and the third gate electrode.

19. The electronic device of claim 18, wherein substantially no discontinuous storage elements lie between the first wall of the trench and the first gate electrode.

20. An electronic device comprising:

a substrate including a trench having a bottom and a first wall;

a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench;

a second gate electrode overlying the substrate outside of the trench;

a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench;

a first source/drain region lying within the substrate below the bottom of the trench and adjacent to the third gate electrode; and

a second source/drain region lying within the substrate outside of the trench and adjacent to the second gate electrode; and

discontinuous storage elements including a first set and a second set of discontinuous storage elements,

wherein;

the first set of discontinuous storage elements lies between the second gate electrode and the substrate;

the second set of discontinuous storage elements lies between the third gate electrode and the bottom of the trench;

the first gate electrode, the second gate electrode, the third gate electrode the first and second sets of discontinuous storage elements, the first source/drain region and the second ion are arts of a first memory cell; and

each of the first gate electrode, the second gate electrode, and third gate electrode has an arc-shaped edge.