Configurable IC with logic resources with offset connections

• US 7,839,166 B2
• Filed: 09/17/2007
• Issued: 11/23/2010
• Est. Priority Date: 06/30/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Hutchings, Brad, Teig, Steven, Huang, Randy Renfu
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/856,214
• Publication Number:
  US 20080061823A1
• Time in Patent Office: 1,163 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Some embodiments provide an integrated circuit that includes several groups of circuits, each group of circuits includes a set of configurable logic circuits. The integrated circuit has at least one direct connection, without any intervening interconnect circuits, that connects an output of a configurable logic circuit in one group of circuits to another circuit in another group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits. In some embodiments, the direct connection has intervening buffer circuits, but no other intervening circuits.

Claims

1. An integrated circuit (IC) comprising:

a) a plurality of groups of circuits in an arrangement of groups of circuits, each group of circuits comprising a set of configurable logic circuits; and

b) a direct connection that connects an output of a first configurable logic circuit of a first group of circuits to an input of a second circuit of a second group of circuits that does not neighbor the first group of circuits and is not aligned with the first group of circuits in the arrangement of groups of circuits, wherein the direct connection does not have any intervening interconnect circuits.

2. An integrated circuit (IC) comprising:

a) a plurality of groups of circuits in an arrangement of groups of circuits, each group of circuits comprising a set of configurable logic circuits; and

b) a direct connection that connects an output of a first configurable logic circuit of a first group of circuits to a second circuit of a second group of circuits that does not neighbor the first group of circuits and is not aligned with the first group of circuits in the arrangement of groups of circuits, wherein said direct connection has no intervening circuits that are not buffer circuits.

3. The IC of claim 2, wherein each of a plurality of configurable logic circuits of the first group of circuits have at least one direct connection with at least one circuit of another group of circuits, wherein said other group of circuits does not neighbor the first group of circuits and is not aligned with the first group of circuits in the arrangement of groups of circuits.

4. The IC of claim 3, wherein the arrangement of groups of circuits comprises an array with columns and rows of groups of circuits, wherein two groups of circuits are not aligned when they are not in the same row and are not in the same column.

5. The IC of claim 2, wherein the second circuit is an interconnect circuit.

6. The IC of claim 2, wherein the second circuit is for receiving output of the first configurable logic circuit through the direct connection.

7. The IC of claim 2, wherein the second circuit is a logic circuit.

8. The IC of claim 2, wherein the second circuit is a configurable input-select circuit for receiving the output of the first configurable logic circuit through the direct connection.

9. The IC of claim 2, wherein each of a plurality of logic circuits of each particular group of circuits in a set of groups of circuits has at least one direct connection with at least one other circuit of another group of circuits that does not neighbor the particular group of circuits and is not aligned with the particular group of circuits in the arrangement of groups of circuits.

10. The IC of claim 2, wherein the direct connection comprises at least one intervening buffer circuit.

11. The IC of claim 2, wherein the direct connection does not include any intervening buffer circuits.

12. An integrated circuit (IC) comprising:

a) a plurality of groups of circuits in an arrangement of groups of circuits, each group of circuits of said plurality of groups of circuits comprising;

i) a set of configurable logic circuits; and

ii) a set of configurable interconnect circuits; and

b) a direct connection that traverses from an output of a first logic circuit of a first group of circuits to an interconnect circuit of a second group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits in the arrangement of groups of circuits, wherein the direct connection comprises at least one buffer circuit and does not include any intervening interconnect circuits.

13. The IC of claim 12 further comprising a plurality of direct connections between interconnect circuits of the first group of circuits and at least one circuit of another group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits.

14. The IC of claim 12, wherein the interconnect circuit of the second group of circuits is a configurable input-select circuit for receiving inputs and supplying a sub-set of the received inputs to a configurable logic circuit of the second group of circuits.

15. The IC of claim 12, wherein each of a plurality of interconnect circuits of each particular group of circuits of said plurality of groups of circuits has at least one direct connection with at least one other circuit of another group of circuits that does not neighbor the particular group of circuits and that is not aligned with the particular group of circuits in the arrangement of groups of circuits.

16. The IC of claim 12, wherein the arrangement of groups of circuits comprises horizontally and vertically aligned groups of circuits, wherein two groups of circuits are not aligned when they are not horizontally aligned and are not vertically aligned.

17. The IC of claim 12, wherein the interconnect circuit of the second group of circuits is a routing interconnect circuit.

18. The IC of claim 17, wherein the routing interconnect circuit is for receiving inputs and supplying a sub-set of those inputs to a configurable input-select circuit for receiving inputs and supplying a sub-set of the inputs received by the input-select circuit to a configurable logic circuit of the second group of circuits.

19. The IC of claim 17, wherein the routing interconnect circuit is for receiving inputs and supplying a sub-set of those inputs to an input of a circuit in a third group of circuits through a direct connection that does not include any intervening interconnect circuits.

20. An integrated circuit (IC) comprising:

a) a plurality of groups of circuits in an arrangement of groups of circuits, each group of circuits comprising a set of configurable logic circuits;

b) a direct connection that connects an output of a first configurable logic circuit of a first group of circuits to an input of a second circuit of a second group of circuits that does not neighbor the first group of circuits and is not aligned with the first group of circuits in the arrangement of groups of circuits, wherein the direct connection does not have any intervening configurable circuits.

21. The IC of claim 20 further comprising input-select circuits in the second group of circuits.

22. The IC of claim 21, wherein the second circuit is one of the input-select circuits.

23. The IC of claim 22, wherein an output of the second circuit is connected to an input of a third logic circuit.