Acquisition of extended display identification data (EDID) using inter-IC (I2C) protocol

• US 7,839,409 B2
• Filed: 02/18/2005
• Issued: 11/23/2010
• Est. Priority Date: 10/18/2004
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Inventors: Noorbakhsh, Ali, Lattanzi, John, Keene, David, Chilukuri, Ram
• Primary Examiner(s): Tung; Kee M
• Assistant Examiner(s): CRAWFORD, JACINTA M
• Application Number:
  US11/060,862
• Publication Number:
  US 20060082584A1
• Time in Patent Office: 2,104 Days
• Field of Search: 345/100, 345/581, 345/531, 345/520, 345/558
• US Class Current: 345/531
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an I2C data bus each coupled to a host device, a method of transferring EDID from the memory device over the I2C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Claims

1. A method, executed in a display controller, of transferring extended display identification data (EDID) from a memory device over an I2C data bus to a requesting data port, wherein a number of data ports, a processor, and a plurality of client devices are connected to the I2C data bus, and wherein the data ports are coupleable to a host device, the method comprising:

receiving an EDID read request from the requesting data port;

passing the EDID read request to the memory device;

transferring the requested EDID from the memory device to a data buffer by way of the I2C data bus;

receiving a memory access request from a requesting client device;

reading the requested EDID from the data buffer in a byte-by-byte manner;

sending each byte of data to the requesting data port for bit-by-bit transmission to the host device under control of an I2C clock signal of the requesting data port concurrently with servicing the requesting client device memory access request, wherein the requesting data port and the requesting client device are each provided access to the memory device as needed without holding the I2C clock signal of the requesting data port (clock stretching), thereby concurrently maintaining compliance to the VESA standard and I2C compliance.

2. A method as recited in claim 1, further comprising:

determining if the data buffer is almost empty.

3. A method as recited in claim 2, further comprising:

if the data buffer is almost empty, then

posting an almost empty flag indicating that the data buffer is almost empty;

reading the almost empty flag by the processor; and

granting access of the memory device to the requesting data port only.

4. A method as recited in claim 3, further comprising:

retrieving data from the memory device to the data buffer until the data buffer is full;

resetting the almost empty flag; and

granting the processor memory access only.

5. A method as recited in claim 1, wherein the data buffer is a FIFO.

6. An extended display identification data (EDID)-compatible display controller comprising:

a number of bi-directional data ports configured to be coupled to a host device;

a processor configured to process executable instructions and associated data and to generate processor memory access requests;

a memory device configured to store EDID and the executable instructions and associated data;

an I2C data bus coupling each of the data ports to the memory device; and

a data buffer coupled to the memory device and the I2C bus;

wherein the EDID-compatible display controller is configured to be coupled to a VESA-compliant display; and

wherein the executable instructions, if executed, cause the EDID-compatible display controller to concurrently service an EDID read request from a requesting one of the data ports and a processor memory access request without clock stretching by;

passing the EDID from the memory device to the data buffer over the I2C data bus;

granting only the processor memory access; and

passing the EDID from the data buffer to the requesting one of the data ports over the I2C data bus in a byte-by-byte manner, thereby providing an I2C data transfer while maintaining VESA compliance.

7. The EDID-compatible display controller of claim 6, further comprising a data buffer empty flag generator configured to set a data buffer empty flag indicating that the data buffer is almost empty.

8. The EDID-compatible display controller of claim 7, wherein the executable instructions further include instructions that, if executed when the data buffer empty flag has been set, cause the EDID-compatible display controller to:

grant only the requesting data port memory access;

retrieve the requested EDID from the memory device to the data buffer until the data buffer is full;

reset the data buffer empty flag; and

grant only the processor memory access.

9. The EDID-compatible display controller of claim 8, wherein the data buffer is a FIFO.