Soft errors handling in EEPROM devices

• US 7,839,685 B2
• Filed: 10/01/2009
• Issued: 11/23/2010
• Est. Priority Date: 05/20/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Craig, Jeffrey, Auclair, Daniel L., Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Norman, Robert D.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US12/572,098
• Publication Number:
  US 20100020616A1
• Time in Patent Office: 418 Days
• Field of Search: 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1. A method of operating a memory system, the memory system including an array of non-volatile memory cells, read and write circuitry connectable to the array, ECC logic, and buffer memory, the method comprising:

writing a set of data and corresponding ECC data by the write circuitry to a plurality of the memory cells;

subsequently performing a read operation of the plurality of the memory cells by the read circuitry using normal read values for distinguishing between the data states;

transferring the result of the read operation to the buffer memory;

using the ECC logic to determine whether the result of the read operation has an uncorrectable amount of error; and

in response to determining that the result of the read operation has an uncorrectable amount of error, performing a read operation of the plurality of the memory cells by the read circuitry using shifted read values for distinguishing between the data states.

2. The method claim 1, further comprising:

transferring the result of the read operation using shifted read values to the buffer memory; and

using the ECC logic to determine whether the result of the read operation using shifted read values has an uncorrectable amount of error.

3. The method of claims 2, further comprising:

in response to determining that the result of the read operation using shifted read values does not have an uncorrectable amount of error, correcting the set of data using the corresponding ECC data.

4. The method of claim 3, further comprising:

subsequently writing the corrected set of data by the write circuitry into cells of the memory array.

5. The method of claim 2, further comprising:

in response to determining that the result of the read operation using shifted read values has an uncorrectable amount of error, performing a read operation of the plurality of the memory cells by the read circuitry using a further shifted read values for distinguishing between the data states.

6. The method of claim 1, wherein the write circuitry writes the memory cells into one of two memory states.

7. The method of claim 1, wherein the write circuitry writes the memory cells into one of more than two memory states.

8. The method of claim 1, wherein the read values include a control gate voltage and the shifted read values are higher than the normal read values.

9. The method of claim 1, wherein the read values include a control gate voltage and the shifted read values are lower than the normal read values.

10. A memory system comprising:

an array of non-volatile memory cells;

read and write circuitry connectable to the array, and

ECC logic, wherein in response to the ECC logic determining that the result of a read operation by the read circuitry using normal read values for distinguishing between the data states has an uncorrectable amount of error, the memory system performs a read operation by the read circuitry using shifted read values for distinguishing between the data states.

11. The memory system of claim 10, wherein the ECC logic subsequently determines whether the result of the read operation using shifted read values has an uncorrectable amount of error.

12. The memory system of claim 11, wherein in response to determining that the result of the read operation using shifted read values does not have an uncorrectable amount of error, correcting the read data using corresponding ECC data.

13. The memory system of claim 12, wherein the memory system writes the corrected data by the write circuitry into cells of the memory circuit.

14. The memory system of claim 11, wherein in response to determining that the result of the read operation using shifted read values has an uncorrectable amount of error, the memory system performs a read operation using a further shifted read values for distinguishing between the data states.

15. The method of claim 10, wherein the write circuitry writes the memory cells into one of two memory states.

16. The method of claim 10, wherein the write circuitry writes the memory cells into one of more than two memory states.

17. The memory system of claim 10, wherein the read values include a control gate voltage and the shifted read values are higher than the normal read values.

18. The memory system of claim 10, wherein the read values include a control gate voltage and the shifted read values are lower than the normal read values.