High temperature methods for enhancing retention characteristics of memory devices

• US 7,839,695 B2
• Filed: 04/27/2007
• Issued: 11/23/2010
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hsu, Tzu Hsuan, Wu, Chao-I
• Primary Examiner(s): Nguyen; Dang T
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US11/741,053
• Publication Number:
  US 20080268659A1
• Time in Patent Office: 1,306 Days
• Field of Search: 365/185.02, 365/185.09, 365/185.22, 365/185.24, 365/185.28, 365/201
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors

Abstract

Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.

Claims

1. A method for improving retention characteristics of a memory device including a plurality of memory cells, comprising:

baking the plurality of memory cells at a temperature level for a sufficient duration to cause shallow trapped charges to be expelled from the plurality of memory cells;

verifying the plurality of memory cells to determine if written data in memory cells are still the same; and

if the plurality of memory cells do not pass the verify step, reprogramming the plurality of 0-state memory cells to the high voltage threshold Vt state again, and further comprising before the reprogramming step, determining whether the number of times that the memory cells have been reprogrammed by the reprogramming step, exceeds N number of times.

2. The method of claim 1, prior to the baking step, further comprising programming the plurality of memory cells by writing data to the plurality of memory cells from a low-Vt state to a high voltage threshold state.

3. The method of claim 1, wherein the baking step comprises baking the memory cells at the temperature level of about 150°

C. or higher.

4. The method of claim 1, wherein the baking step comprises baking the memory cells at the temperature level of about 250°

C. or higher.

5. The method of claim 1, after the reprogramming step, further comprising returning to the baking step.

6. The method of claim 1, wherein the plurality of memory cells comprises uncycled memory cells that have not been previously undergoing program and erase cycles.

7. A method for improving retention characteristics of a memory device including a plurality of memory cells, comprising:

programming and erasing the plurality of memory cells;

excluding one or more memory cells in the plurality of memory cells that do not pass the programming and erasing steps;

baking the memory cells at a temperature level for a sufficient duration to cause shallow trapped charges to be expelled from the memory cells;

verifying the plurality of memory cells to determine if written data in the memory cells are still the same; and

if the memory cells do not pass the verify step, reprogramming the plurality of 0-state memory cells to the high voltage threshold Vt state, and further comprising before the reprogramming step, determining that the number of times that the memory cells have been reprogrammed by the reprogramming step, exceeds N number of times.

8. The method of claim 7, prior to the baking step, further comprising programming the plurality of memory cells by writing data to the plurality of memory cells from a low-Vt to a high voltage threshold state.

9. The method of claim 7, wherein the baking step comprises baking the memory cells at the temperature level of about 150°

C. or higher.

10. The method of claim 7, wherein the baking step comprises baking the memory cells at the temperature level of about 250°

C. or higher.

11. The method of claim 7, after the reprogramming step, further comprising returning to the baking step.