Method and system for determining a number of data packets required to transport a data block

• US 7,839,936 B2
• Filed: 05/05/2005
• Issued: 11/23/2010
• Est. Priority Date: 05/05/2005
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Vacanti, Michael
• Primary Examiner(s): RAO, ANAND SHASHIKANT
• Application Number:
  US11/123,483
• Publication Number:
  US 20060251121A1
• Time in Patent Office: 2,028 Days
• Field of Search: 37524001-24029
• US Class Current: 375/240.26
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation

Abstract

A method and system for determining a number of non-power of two sized data packets required to transport a data block. A data block size is shifted rightward by a number of bits equal to a base-two exponent of a divisor, with the bits remaining stored as a first value, and the bits removed stored as a second value. At least one binary shift is performed to calculate a third and fourth value. The fourth value is shifted and added to the second value to calculate a fifth value. At least one comparison is performed on the fifth value to process a sixth and seventh value. A number of non-power of two sized data packets is determined by summing the first, third, and sixth values, then adding one if the seventh value is not zero.

Claims

1. A process to determine a number of data packets required to transport a data block, wherein said data packets comprise a non-power of two number of bytes, said process comprising:

shifting a binary equivalent of a decimal size of the data block rightward by a number of bits equal to an exponent of a decimal divisor as a power of two, wherein the decimal divisor is equal to a next power of two larger than the decimal size of the data packets;

storing bits remaining from the rightward shifting of the block size as a first value, and storing bits removed by the rightward shifting of the block size as a second value;

shifting the first value rightward by a number of bits equal to one less than the exponent of the decimal divisor as the power of two;

storing bits remaining from the rightward shifting of the first value as a third value and storing a sum of the third value and bits removed by the rightward shifting of the first value as a fourth value;

shifting the fourth value and adding the second value to calculate a fifth value;

performing at least one comparison on the fifth value to process a sixth value and a seventh value; and

determining the number of data packets required to transport the data block by summing the first value, third value, and sixth value, and adding one if the seventh value is not zero.

2. The process as recited in claim 1, wherein the divisor is greater than the non-power of two sized data packet by a power of two.

3. The process as recited in claim 1, wherein the non-power of two data packets each comprise sixty-two bytes and the divisor comprises sixty-four bytes.

4. The process of claim 1, wherein the process includes processing a third value and fourth value including:

using a looping comparator; and

providing a starting argument for said looping comparator based on a comparison to a width in bits of the first value.

5. The process of claim 1, wherein said shifting the fourth value and adding the second value to calculate a fifth value further comprises:

determining a difference between the divisor and the non-power of two sized data packet; and

shifting the fourth value leftward by a number of binary shifts equal to said difference.

6. The process as recited in claim 1, wherein said performing at least one comparison on the fifth value to process a sixth value and a seventh value further comprises:

utilizing a priority encoder.

7. A computer-readable medium having computer executable instructions that, when executed, perform a process to determine a number of non-power of two sized data packets required to transport a data block, said process comprising:

shifting a binary equivalent of a decimal size of the data block rightward by a number of bits equal to an exponent of a decimal divisor as a power of two, wherein the decimal divisor is equal to a next power of two larger than the decimal size of the data packets;

storing bits remaining from the rightward shifting of the block size as a first value, and storing bits removed by the rightward shifting of the block size as a second value;

shifting the first value rightward by a number of bits equal to one less than the exponent of the decimal divisor as the power of two;

storing bits remaining from the rightward shifting of the first value as a third value and storing a sum of the third value and bits removed by the rightward shifting of the first value as a fourth value;

shifting the fourth value and adding the second value to calculate a fifth value;

performing at least one comparison on the fifth value to process a sixth value and a seventh value; and

determining the number of data packets required to transport the data block by summing the first value, third value, and sixth value, and adding one if the seventh value is not zero.

8. The process as recited in claim 7, wherein the divisor is greater than the non-power of two sized data packet by a power of two.

9. The process as recited in claim 7, wherein the non-power of two data packets each comprise sixty-two bytes and the divisor comprises sixty-four bytes.

10. The process of claim 7, wherein the process includes processing a third value and fourth value including:

using a looping comparator; and

providing a starting argument for said looping comparator based on a comparison to a width in bits of the first value.

11. The process of claim 7, wherein said shifting the fourth value and adding the second value to calculate a fifth value further comprises:

determining a difference between the divisor and the non-power of two sized data packet; and

shifting the fourth value leftward by a number of binary shifts equal to said difference.

12. The process as recited in claim 7, wherein said processing a sixth value and a seventh value from said fifth value through a plurality of comparisons comprises:

utilizing a priority encoder.

13. A computer system comprising:

a communications link;

a processor coupled to the communications link, said processor capable of executing a process to determine a number of non-power of two sized data packets required to transport a data block;

a shifter coupled to said processor, said shifter to;

shift a binary equivalent of a decimal size of a data block rightward by a number of bits equal to an exponent of a decimal devisor as a power of two, wherein the decimal devisor is equal to a next power of two larger than a decimal size of the data packets;

shift a first value rightward by a number of bits equal to one less than the exponent of the decimal divisor as the power of two, wherein the first value comprises bits remaining from the rightward shift of the block size; and

shift a fourth value;

a memory coupled to said shifter, said memory to;

store the first value, and bits removed by the rightward shifting as a second value; and

store bits remaining from the rightward shift of the first value as a third value and store a sum of the third value and bits removed by the rightward shift of the first value as the fourth value;

an adder coupled to said logic to;

add the second value to the shifted fourth value to calculate a fifth value; and

add the first value, the third value, and a sixth value and adding one if a seventh value is not zero; and

logic coupled to said memory and to said adder, said logic to;

perform at least one comparison on the fifth value to process the sixth value and the seventh value; and

determine the number of data packets required to transport the data block according to the sum of the first value, third value, and sixth value and the addition of one if the seventh value is not zero.

14. The computer system of claim 13, wherein said processor comprises:

an Application Specific Integrated Circuit (ASIC).

15. The computer system of claim 13, further comprising:

a plurality of communications links, wherein said processor is coupled to the plurality of communications links.

16. The process of claim 13, wherein the non-power of two data packets each comprise sixty-two bytes.

17. The process of claim 13, wherein said shifter to shift a data block size by a number of bits further comprises:

a shifter to shift a data block size by a number of bits equal to a base-two exponent of a divisor, wherein the divisor is greater than the non-power of two sized data packet by a power of two.

18. The process of claim 13, wherein said logic further comprises:

logic to compute the third value and the fourth value from said first value with a looping comparator.

19. The process of claim 13, wherein said logic further comprises:

logic to compute the remainder and the sixth value with a priority encoder.