Semiconductor device

• US 7,840,188 B2
• Filed: 10/24/2007
• Issued: 11/23/2010
• Est. Priority Date: 10/31/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Nguyen; Tu X
• Application Number:
  US11/976,378
• Publication Number:
  US 20080101267A1
• Time in Patent Office: 1,126 Days
• Field of Search: 455/73, 455/574, 455/121, 713/340, 713/300, 713/320
• US Class Current: 455/73
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost.

Claims

1. A semiconductor device comprising:

a plurality of CPUs;

a router circuit;

a thread control circuit connected to the router circuit through a first bus; and

an external device controller connected to the router circuit through a second bus,

wherein each of the plurality of CPUs includes;

a first wireless circuit which includes a first antenna circuit, a first demodulation circuit, and a first modulation circuit; and

a CPU core which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register,

wherein the router circuit includes;

a data processing circuit; and

a second wireless circuit which includes a second antenna circuit, a second demodulation circuit, and a second modulation circuit,

wherein the first wireless circuit and the second wireless circuit each are configured to transmit and receive data between the CPU and the router circuit wirelessly,

wherein the first wireless circuit is configured to transmit data to the second wireless circuit by a backscattering method,

wherein the data processing circuit is configured to process and store first data to be transmitted to or received from each of the plurality of CPUs, second data to be transmitted to or received from the thread control circuit, and third data to be transmitted to or received from the external device controller,

wherein the thread control circuit is configured to allocate an instruction to be executed by the CPU core to the CPU core, and

wherein the external device controller is configured to transmit and receive data to and from an external device which is connected through an external data input line and an external data output line.

2. The semiconductor device according to claim 1, wherein the external device controller is a DRAM controller.

3. The semiconductor device according to claim 1, wherein the external device controller is a PCI bus controller.

4. The semiconductor device according to claim 1, wherein the external device controller is a USB controller.

5. The semiconductor device according to claim 1, wherein each of the plurality of CPUs is formed using a thin film transistor which includes as an active layer a semiconductor thin film formed over a substrate having an insulating surface.

6. The semiconductor device according to claim 5, wherein the substrate having an insulating surface is one selected from the group consisting of a glass substrate, a plastic substrate, and an SOI substrate.

7. A semiconductor device comprising:

a plurality of CPUs;

a router circuit;

a thread control circuit connected to the router circuit through a first bus; and

an external device controller connected to the router circuit through a second bus,

wherein each of the plurality of CPUs includes;

a first wireless circuit which includes a first antenna circuit, a first demodulation circuit, a first modulation circuit, and a power supply circuit; and

a CPU core which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register,

wherein the power supply circuit is configured to generate a power supply voltage to be supplied to the CPU from a wireless signal received by the first antenna circuit,

wherein the router circuit includes;

a data processing circuit; and

a second wireless circuit which includes a second antenna circuit, a second demodulation circuit, and a second modulation circuit,

wherein the first wireless circuit and the second wireless circuit are configured to transmit and receive data between the CPU and the router circuit wirelessly,

wherein the first wireless circuit is configured to transmit data to the second wireless circuit by a backscattering method,

wherein the data processing circuit is configured to process and store first data to be transmitted to or received from each of the plurality of CPUs, second data to be transmitted to or received from the thread control circuit, and third data to be transmitted to or received from the external device controller,

wherein the thread control circuit is configured to allocate an instruction to be executed by the CPU core to the CPU core, and

wherein the external device controller is configured to transmit and receive data to and from an external device which is connected through an external data input line and an external data output line.

8. The semiconductor device according to claim 7, wherein the external device controller is a DRAM controller.

9. The semiconductor device according to claim 7, wherein the external device controller is a PCI bus controller.

10. The semiconductor device according to claim 7, wherein the external device controller is a USB controller.

11. The semiconductor device according to claim 7, wherein each of the plurality of CPUs is formed using a thin film transistor which includes as an active layer a semiconductor thin film formed over a substrate having an insulating surface.

12. The semiconductor device according to claim 11, wherein the substrate having an insulating surface is one selected from the group consisting of a glass substrate, a plastic substrate, and an SOI substrate.

13. A semiconductor device comprising:

a plurality of CPUs;

a router circuit;

a thread control circuit connected to the router circuit through a first bus; and

an external device controller connected to the router circuit through a second bus,

wherein each of the plurality of CPUs includes;

a first wireless circuit which includes a first antenna circuit, a third antenna circuit, a first demodulation circuit, a first modulation circuit, a first power supply circuit, and a second power supply circuit; and

a CPU core which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register,

wherein the first power supply circuit is configured to generate a power supply voltage to be supplied to the CPU from a first wireless signal received by the first antenna circuit,

wherein the second power supply circuit includes a step-up circuit and is configured to generate a power supply voltage to be supplied to the CPU from a second wireless signal received by the third antenna circuit,

wherein the router circuit includes a data processing circuit and a second wireless circuit which includes a second antenna circuit, a second demodulation circuit, and a second modulation circuit,

wherein the first wireless circuit and the second wireless circuit are configured to transmit and receive data between the CPU and the router circuit wirelessly,

wherein the first wireless circuit is configured to transmit data to the second wireless circuit by a backscattering method,

wherein the data processing circuit is configured to process and store first data to be transmitted to or received from each of the plurality of CPUs, second data to be transmitted to or received from the thread control circuit, and third data to be transmitted to or received from the external device controller,

wherein the thread control circuit are configured to allocate an instruction to be executed by the CPU core to the CPU core, and

wherein the external device controller is configured to transmit and receive data to and from an external device which is connected through an external data input line and an external data output line.

14. The semiconductor device according to claim 13, wherein the external device controller is a DRAM controller.

15. The semiconductor device according to claim 13, wherein the external device controller is a PCI bus controller.

16. The semiconductor device according to claim 13, wherein the external device controller is a USB controller.

17. The semiconductor device according to claim 13, wherein each of the plurality of CPUs is formed using a thin film transistor which includes as an active layer a semiconductor thin film formed over a substrate having an insulating surface.

18. The semiconductor device according to claim 17, wherein the substrate having an insulating surface is one selected from the group consisting of a glass substrate, a plastic substrate, and an SOI substrate.