Method and system for high speed options pricing

• US 7,840,482 B2
• Filed: 06/08/2007
• Issued: 11/23/2010
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Exegy Incorporated
• Inventors: Parsons, Scott, Taylor, David E., Franklin, Mark A., Singla, Naveen
• Primary Examiner(s): Patel; Jagdish N
• Assistant Examiner(s): HAMILTON, SARA CHANDLER
• Application Number:
  US11/760,211
• Publication Number:
  US 20070294157A1
• Time in Patent Office: 1,264 Days
• Field of Search: 705/36, 705/37
• US Class Current: 705/37
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. A parallel/pipelined architecture is disclosed for computing an implied volatility in connection with an option. Parallel/pipelined architectures are also disclosed for computing an option'"'"'s theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations.

Claims

1. A device for processing financial market data, the device comprising:

a reconfigurable logic device that is configured to (1) receive a data stream comprising financial market data and (2) perform a plurality of options pricing operations in parallel on at least a portion of the received data stream, wherein the reconfigurable logic device comprises a plurality of pipelined computational modules deployed in firmware for computing an implied volatility for each of a plurality of options over a plurality of iterations, wherein each firmware computational module in the pipeline corresponds to a different iteration of the implied volatility computation such that the firmware computational modules in the pipeline are configured to simultaneously perform different iterations of the implied volatility computation for different options, and wherein the pipeline is further configured to return an implied volatility for each option after being found as a result of the iterative computations.

2. The device of claim 1 wherein each firmware computational module in the pipeline is configured to compute a plurality of theoretical fair market prices for an option in parallel.

3. The device of claim 2 wherein each firmware computational module comprises a plurality of parallel computational units, each parallel computational unit configured to compute a theoretical fair market price for an option based on a volatility value, wherein the parallel computational units of a firmware computational module are seeded with different volatility values.

4. The device of claim 3 wherein each parallel computational unit is further configured to compute the theoretical fair market prices for the options based on a Cox-Ross-Rubinstein (CRR) option pricing model.

5. The device of claim 3 wherein the parallel computational units of the firmware computational module corresponding to a first iteration of the implied volatility computation are configured to compute a plurality of theoretical fair market prices for a band of volatility values, and wherein the parallel computational units of the firmware computational modules corresponding to subsequent iterations of the implied volatility computation are configured to compute a plurality of theoretical fair market prices for progressively narrower bands of volatility values.

6. The device of claim 1 wherein each firmware computational module in the pipeline is configured to generate a signal indicative of whether it has computed the implied volatility for an option, the reconfigurable logic device further comprising a control unit, the control unit configured to (1) read the generated signals from the firmware computational modules in the pipeline to determine whether the implied volatility for an option has been computed, and (2) output the computed implied volatility in response to the reading of the generated signals even if the firmware computational module that computed the implied volatility is not the final firmware computational module of the pipeline.

7. The device of claim 1 wherein each firmware computational module in the pipeline is configured to compute a theoretical fair market price for an option using a lookup table indexed by a volatility for the option, the lookup table being configured to store a plurality of precomputed parameters for a plurality of different volatility values, the precomputed parameters for use by that firmware computational module in the computation of the theoretical fair market price.

8. The device of claim 7 wherein the lookup table is external to the reconfigurable logic device.

9. The device of claim 1 wherein each firmware computational module in the pipeline is configured to compute a theoretical fair market price for an option, the reconfigurable logic device comprising a plurality of pipelined stages for directly computing a plurality of constituent terms used in the theoretical fair market price computation, wherein a plurality of the pipelined stages comprise a plurality of parallel computational units.

10. The device of claim 9 wherein the pipelined stages are configured to perform the theoretical fair market price computation based on a binomial option pricing model.

11. The device of claim 1 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

12. A method for processing financial market data, the method comprising:

receiving, by a reconfigurable logic device, a data stream comprising financial market data; and

performing, by the reconfigurable logic device, a plurality of options pricing operations in parallel on at least a portion of the received data stream, wherein the performing step comprises computing, by a plurality of pipelined computational modules deployed on the reconfigurable logic device in firmware, an implied volatility for each of a plurality of options over a plurality of iterations, wherein each firmware computational module in the pipeline corresponds to a different iteration of the implied volatility computation such that the firmware computational modules in the pipeline simultaneously perform different iterations of the implied volatility computation for different options and wherein the pipeline returns the implied volatility for each option after being found as a result of the iterative computations.

13. The method of claim 12 wherein the performing step further comprises each firmware computational module in the pipeline computing a plurality of theoretical fair market prices for an option in parallel.

14. The method of claim 13 wherein each firmware computational module comprises a plurality of parallel computational units, wherein the performing step further comprises:

seeding the parallel computational units of a firmware computational module with different volatility values; and

computing, with each parallel computational unit, a theoretical fair market price for an option based on a seeded volatility value.

15. The method of claim 14 wherein the step of computing the theoretical fair market prices comprises computing the theoretical fair market prices for the options based on a Cox-Ross-Rubinstein (CRR) option pricing model.

16. The method of claim 14 wherein the performing step further comprises:

computing, with the parallel computational units of the firmware computational module corresponding to a first iteration of the implied volatility computation, a plurality of theoretical fair market prices for a band of volatility values; and

computing, with the parallel computational units of the firmware computational modules corresponding to subsequent iterations of the implied volatility computation, a plurality of theoretical fair market prices for progressively narrower bands of volatility values.

17. The method of claim 12 wherein each firmware computational module in the pipeline generates a signal indicative of whether it has computed the implied volatility for an option, the reconfigurable logic device further comprising a control unit, the control unit (1) reading the generated signals from the firmware computational modules in the pipeline to determine whether the implied volatility for an option has been computed, and (2) outputting the computed implied volatility in response to the reading of the generated signals even if the firmware computational module that computed the implied volatility is not the final firmware computational module of the pipeline.

18. The method of claim 12 wherein each firmware computational module in the pipeline computes a theoretical fair market price for an option using a lookup table indexed by a volatility for the option, the lookup table storing a plurality of precomputed parameters for a plurality of different volatility values, the precomputed parameters for use by that firmware computational module in the computation of the theoretical fair market price.

19. The method of claim 18 wherein the lookup table is external to the reconfigurable logic device.

20. The method of claim 12 wherein each firmware computational module in the pipeline computes a theoretical fair market price for an option by directly computing, with a plurality of pipelined stages, a plurality of constituent terms used in the theoretical fair market price computation, wherein a plurality of the pipelined stages comprise a plurality of parallel computational units.

21. The method of claim 20 wherein the step of computing the theoretical fair market price comprises performing the theoretical fair market price computation based on a binomial option pricing model.

22. The method of claim 12 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).