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Buffered memory module with multiple memory device data interface ports supporting double the memory capacity

  • US 7,840,748 B2
  • Filed: 08/31/2007
  • Issued: 11/23/2010
  • Est. Priority Date: 08/31/2007
  • Status: Expired due to Fees
First Claim
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1. A memory system, comprising:

  • a memory controller; and

    at least one memory module coupled to the memory controller, wherein each memory module of the at least one memory module comprises at least one memory hub device integrated in the memory module, and wherein each memory hub device of the at least one memory hub device in the memory module comprises;

    a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module;

    a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module wherein the first memory device data interface is separate from the second memory device data interface, and wherein;

    the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the first and second memory device data interfaces, andthe first memory device data interface and the second memory device data interface process a plurality of access requests in parallel at a same time, thereby increasing a bandwidth for accessing the first and second set of memory devices relative to a memory module having a single memory device data interface; and

    a memory hub controller coupled to the first memory device data interface and the second memory device data interface, wherein;

    the memory hub controller responds to a plurality of access request packets from one of the memory controller or a downstream memory hub device of another memory module by responsively driving the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time,responsive to receiving a read data access request and a write data access request, the memory hub controller drives the read data flow selector to a first multiplexer of the memory hub device to select outputting read data directly from one or more of the first memory device data interface, the second memory device data interface, or a read data queue, and drives either the first write data flow selector to a second multiplexer or the second write data flow selector to a third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device,responsive to receiving two write data access requests the memory hub controller drives the first write data flow selector to the second multiplexer and the second write data flow selector to the third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, andthe second multiplexer provides an output to the first memory device data interface and the third multiplexer provides an output to the second memory device data interface.

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