Buffered memory module with multiple memory device data interface ports supporting double the memory capacity

• US 7,840,748 B2
• Filed: 08/31/2007
• Issued: 11/23/2010
• Est. Priority Date: 08/31/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Primary Examiner(s): Kim; Matt
• Assistant Examiner(s): PATEL, KAUSHIKKUMAR M
• Application Number:
  US11/848,318
• Publication Number:
  US 20090063787A1
• Time in Patent Office: 1,180 Days
• Field of Search: None
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Claims

1. A memory system, comprising:

a memory controller; and

at least one memory module coupled to the memory controller, wherein each memory module of the at least one memory module comprises at least one memory hub device integrated in the memory module, and wherein each memory hub device of the at least one memory hub device in the memory module comprises;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module;

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module wherein the first memory device data interface is separate from the second memory device data interface, and wherein;

the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the first and second memory device data interfaces, and

the first memory device data interface and the second memory device data interface process a plurality of access requests in parallel at a same time, thereby increasing a bandwidth for accessing the first and second set of memory devices relative to a memory module having a single memory device data interface; and

a memory hub controller coupled to the first memory device data interface and the second memory device data interface, wherein;

the memory hub controller responds to a plurality of access request packets from one of the memory controller or a downstream memory hub device of another memory module by responsively driving the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time,

responsive to receiving a read data access request and a write data access request, the memory hub controller drives the read data flow selector to a first multiplexer of the memory hub device to select outputting read data directly from one or more of the first memory device data interface, the second memory device data interface, or a read data queue, and drives either the first write data flow selector to a second multiplexer or the second write data flow selector to a third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device,

responsive to receiving two write data access requests the memory hub controller drives the first write data flow selector to the second multiplexer and the second write data flow selector to the third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, and

the second multiplexer provides an output to the first memory device data interface and the third multiplexer provides an output to the second memory device data interface.

2. The memory system of claim 1, wherein the bandwidth for accessing the first and second set of memory devices is approximately twice a bandwidth of the memory module having the single memory device data interface.

3. The memory system of claim 1, wherein the at least one memory module comprises a plurality of memory modules.

4. The memory system of claim 1, wherein each memory module in the at least one memory module comprises a plurality of memory hub devices.

5. The memory system of claim 1 , wherein each memory hub device in the at least one memory hub device comprises:

a third memory device data interface integrated in the memory hub device that communicates with a third set of memory devices integrated in the memory module; and

a fourth memory device data interface integrated in the memory hub device that communicates with a fourth set of memory devices integrated in the memory module.

6. The memory system of claim 1, wherein the memory hub controller, in response to receiving a plurality of write access request packets, issues a first memory write access request to the first set of memory devices via the first memory device data interface and sends first data associated with the first memory write access request by driving the first write data flow selector to the second multiplexer and immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface and sends second data associated with the second memory write access request by driving the second write data flow selector to the third multiplexer.

7. The memory system of claim 1, wherein the memory hub controller, in response to receiving a plurality of read access request packets, issues a first memory read access request to the first set of memory devices via the first memory device data interface and immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface.

8. The memory system of claim 7, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller.

9. The memory system of claim 7, wherein read data from the first memory read access request and the second memory read access request are queued prior to being transferred to the memory controller.

10. The memory system of claim 1, wherein each memory hub device further comprises:

the memory hub controller integrated into the memory hub device; and

the link interface integrated into the memory hub device, wherein the link interface provides a communication path between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the first and second set of memory devices receive and send data via the link interface.

11. The memory system of claim 10, wherein each memory hub device further comprises:

the first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller.

12. The memory system of claim 10, wherein each memory hub device further comprises:

the second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide first write data from the link interface to the first set of memory devices based on a first control signal from the memory hub controller; and

the third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the third multiplexer being provided so as to provide second write data from the link interface to the second set of memory devices based on a second control signal from the memory hub controller.

13. A method of accessing memory devices of a memory module, comprising:

receiving, by a link interface of a memory hub device integrated in the memory module, plurality of access requests for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module, wherein the plurality of access requests are received from a memory controller coupled to the memory module;

sending, by the link interface, the plurality of access requests to a memory hub controller integrated into the memory hub device;

selecting, the memory hub controller one or both of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the plurality of access requests;

responsively driving, by the memory hub controller, the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time in response to receiving a plurality of access request packets from one of the memory controller or a downstream memory hub device of another memory module, wherein;

responsive to receiving a read data access request and a write data access request, the memory hub controller drives the read data flow selector to a first multiplexer of the memory hub device to select outputting read data directly from one or more of the first memory device data interface, the second memory device data interface, or a read data queue, and drives either the first write data flow selector to a second multiplexer or the second write data flow selector to a third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device,

responsive to receiving two write data access requests, the memory hub controller drives the first write data flow selector to the second multiplexer and the second write data flow selector to the third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, and

the second multiplexer provides an output to the first memory device data interface and the third multiplexer provides an output to the second memory device data interface; and

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein;

the first memory device data interface communicates with the first set of memory devices,

the second memory device data interface communicates with the second set of memory devices,

the first set of memory devices are separate from the second set of memory devices,

the first memory device data interface is separate from the second memory device data interface, and

the first memory device data interface and the second memory device data interface process access requests in parallel at a same time, thereby increasing a bandwidth for accessing the first and second set of memory devices relative to a memory module having a single memory device data interface.

14. A data processing system, comprising:

a processor; and

a memory controller coupled to the processor;

a memory coupled to the memory controller, wherein the memory comprises at least one memory module and wherein each memory module in the at least one memory module comprises;

at least one memory hub device integrated in the memory module, wherein each memory hub device of the at least one memory hub device in the memory module comprises;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module;

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module wherein the first memory device data interface is separate from the second memory device data interface, and wherein;

the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the first and second memory device data interfaces, and

the first memory device data interface and the second memory device data interface process a plurality of access requests in parallel at a same time, thereby increasing a bandwidth for accessing the first and second set of memory devices relative to a memory module having a single memory device data interface; and

a memory hub controller coupled to the first memory device data interface and the second memory device data interface, wherein;

the memory hub controller responds to a plurality of access request packets from one of the memory controller or a downstream memory hub device of another memory module by responsively driving the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time,

responsive to receiving a read data access request and a write data access request, the memory hub controller drives the read data flow selector to a first multiplexer of the memory hub device to select outputting read data directly from one or more of the first memory device data interface the second memory device data interface, or a read data queue, and drives either the first write data flow selector to a second multiplexer or the second write data flow selector to a third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device,

responsive to receiving two write data access requests, the memory hub controller drives the first write data flow selector to the second multiplexer and the second write data flow selector to the third multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, and

the second multiplexer provides an output to the first memory device data interface and the third multiplexer provides an output to the second memory device data interface.