Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof

• US 7,840,762 B2
• Filed: 08/23/2007
• Issued: 11/23/2010
• Est. Priority Date: 01/17/2007
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Soo-Young, Kim, Yong-Jun, Oh, Chi-Sung, Nam, Kyung-Woo, Kim, Jin-Kuk
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US11/843,877
• Publication Number:
  US 20080170460A1
• Time in Patent Office: 1,188 Days
• Field of Search: None
• US Class Current: 711/149
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Claims

1. A semiconductor memory device having N number of ports, the device comprising:

at least one shared memory area provided in a memory cell array, operationally connected to the N number of ports, and accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one shared memory area, among the N number of ports; and

N number of mailbox areas adjacent to the at least one shared memory for message communication provided in one-to-one correspondence with the N number of ports and accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device.

2. The device of claim 1, wherein N is two, one of the two ports is a first port, and the other of the two ports is a second port.

3. The device of claim 2, wherein each of the two mailbox areas comprises:

at least one first mailbox that is writable and readable through the first port and that is not writable but readable through the second port; and

at least one second mail box that is writable and readable through the second port and that is not writable but readable through the first port.

4. The device of claim 3, further comprising:

a mailbox path controller to set at least one message access path to the two mailbox areas through the first and second ports.

5. The device of claim 4, wherein the two mailbox areas are disposed on both sides of the at least one shared memory area, and the data input/output lines are disposed in parallel over the at least one shared memory area to form a shared path serving as a data access path or a message access path.

6. The device of claim 5, wherein the at least two first mailboxes are classified into at least one first local mailbox capable of being connected to the first port through the shared path and at least one first main mailbox capable of being directly connected to the first port without using the shared path;

and

the at least two second mailboxes are classified into at least one second local mailbox capable of being connected to the second port through the shared path and at least one second main mailbox capable of being directly connected to the second port without using the shared path.

7. The device of claim 6, when the first port has an access right to the at least one shared memory area,

a message writing operation is performed on all of the at least one first main mailbox and the at least one first local mailbox through the first port and is performed on the at least one second main mailbox through the second port, and

a message reading operation is performed on the at least one second main mailbox through the first port and is performed on the at least one first local mailbox through the second port.

8. The device of claim 7, wherein, when the second port has an access right to the at least one shared memory area,

a message writing operation is performed on the at least one first main mailbox through the first port and is performed on the at least one second main mailbox and the at least one second local mailbox through the second port, and

a message reading operation is performed on the at least one second local mailbox through the first port and is performed on the at least one first main mailbox through the second port.

9. The device of claim 8, wherein, during the message reading operation is performed on the at least one second main mailbox through the first port, an operation of updating messages of the at least one second local mailbox with messages of the at least one second main mailbox is performed, and during the message reading operation on the at least one first main mailbox is performed through the second port, an operation of updating messages of the at least one first local mailbox with messages of the at least one first main mailbox is performed.

10. A semiconductor memory device having N number of ports, comprising:

at least one shared memory area provided in a memory cell array, operationally connected to the N number of ports, and accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one shared memory area, among the N number of ports; and

N number of mailbox areas adjacent to the at least one shared memory and accessible through a plurality of message input/output lines, which are provided per port for message communication between the N number of ports, are separately disposed in parallel to the plurality of data input/output lines, and serve as a message access path, when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device.

11. The device of claim 10, wherein the plurality of message input/output lines are disposed over the at least one shared memory area.

12. The device of claim 11, wherein N is two, one of the two ports is a first port, and the other of the two ports is a second port.

13. The device of claim 12, wherein each of the two mailbox areas comprises:

at least one first mailbox that is writable and readable through the first port and that is not writable but readable through the second port; and

at least one second mailbox that is writable and readable through the second port and that is not writable but readable through the first port.

14. The device of claim 13, wherein the number of message input/output lines is equal to the number of mailboxes.

15. The device of claim 13, wherein the at least two first mailboxes include at least one first local mailbox and at least one first main mailbox, the at least one local mailbox forming a first local mailbox block which is capable of being connected to the first port through a first common message input/output line, and the at least one main mailbox forming a first main mailbox block which is capable of being directly connected to the first port without using the first common message input/output line, and

the at least two second mailboxes include at least one second local mailbox and at least one second main mailbox, the at least one second local mailbox forming a second local mailbox block which is capable of being connected to the second port through a second common message input/output line, and the at least one second main mailbox forming a second main mailbox block which is capable of being directly connected to the second port without using the second common message input/output line.

16. The device of claim 15, further comprising:

a mailbox sub-decoder to selectively connect any one of the at least one first local mailbox of the first local mailbox block and any one of the at least one first main mailbox of the first main mailbox block through the first common message input/output line, or selectively connect any one of the at least one second local mailbox of the second local mailbox block and any one of the at least one second main mailbox of the second main mailbox block through the second common message input/output line.

17. The device of claim 16, wherein the at least one first main mailbox and the at least one second local mailbox are coupled to the first port through separate lines, and the at least one first local mailbox and the at least one second main mailbox are coupled to the second port through separate lines.

18. The device of claim 17, wherein messages written to the at least one first main mailbox through the first port are serially transmitted through the first common message input/output line and are written to the at least one first local mailbox, and messages written to the at least one second main mailbox through the second port are serially transmitted through the second common message input/output line and are written to the at least one second local mailbox.

19. The device of claim 18, wherein a message reading operation on any one of the at least two first mailboxes through the second port is performed by accessing to a corresponding first local mailbox, and a message reading operation on any one of the at least two second mailboxes through the first port is performed by accessing to a corresponding second local mailbox.

20. The device of claim 19, wherein the semiconductor memory device comprises:

a plurality of the first local mailbox blocks;

a plurality of the first main mailbox blocks;

a plurality of the second local mailbox blocks; and

a plurality of the second main mailbox blocks.

21. The device of claim 20, further comprising:

a mailbox main decoder to select any one of the first mailbox blocks and any one of the second mailbox blocks so that a mailbox area is accessed through the first or second port.

22. The device of claim 13, wherein the semiconductor memory device comprises:

a plurality of first mailbox blocks each having at least one first mailbox; and

a plurality of second mailbox blocks each having at least one second mailbox.

23. The device of claim 22, wherein the plurality of first mailbox blocks are classified into first local mailbox blocks and first main mailbox blocks, the first local mailbox blocks each including at least one first local mailbox capable of being connected to the first port through at least one first message input/output line provided in one-to-one correspondence with the at least one first local mailbox, and the first main mailbox blocks each including at least one first main mailbox capable of being directly connected to the first port without using the at least one first message input/output line, and

the plurality of second mailbox blocks are classified into second local mailbox blocks and second main mailbox blocks, the second local mailbox blocks each including at least one second local mailbox capable of being connected to the second port through at least one second message input/output line provided in one-to-one correspondence with the at least one second local mailbox, and the second main mailbox blocks each including at least one second main mailbox capable of being directly connected to the second port without using the at least one second message input/output line.

24. The device of claim 23, further comprising:

a mailbox main decoder to select any one of the plurality of first mailbox blocks and any one of the plurality of second mailbox blocks.

25. A method of controlling an access to a mailbox in a semiconductor memory device having a shared memory area accessed through at least two ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device, and adapted to perform a message communication between the at least two ports, the method comprising:

preparing pairs of main and local mailbox blocks as many as the number of ports, each pair of main and local mailbox blocks corresponding to one of the at least two ports, each local mailbox block including a plurality of local mailboxes that each are capable of being connected to a corresponding port through a data access path serving as a shared path for the shared memory area, and each main mailbox block including a plurality of main mailboxes that each are capable of being directly connected to a corresponding port without using the shared path; and

performing a control so that when a predetermined port of the at least two ports has an access right to the shared memory area, a message writing operation on all of main mailboxes and local mailboxes corresponding to the predetermined port and a message reading operation on some main mailboxes, having messages to the predetermined port, among the main mailboxes corresponding to the other ports are performed through the predetermined port, and so that when the predetermined port does not have the access right to the shared memory area, a message writing operation on the main mailboxes corresponding to the predetermined port and a message reading operation on some local mailboxes, having messages to the predetermined port, among the local mailboxes corresponding to the other ports are performed through the predetermined port.

26. The method of claim 25, wherein, while the message reading operation on the some main mailboxes is being performed through the predetermined port, an update operation is performed so that messages in the some main mailboxes are the same as messages of corresponding local mailboxes.

27. A method of controlling an access to a mailbox in a semiconductor memory device having a shared memory area accessed through at least two ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device, and adapted to perform a message communication between the at least two ports, the method comprising:

preparing pair of main and local mailbox blocks as many as the number of ports, each pair of main and local mailbox blocks corresponding to one of the at least two ports, each local mailbox block including a plurality of local mailboxes that are accessible through a common message input/output line separate from data input/output lines for a data access to the shared memory area, and each main mailbox block including a plurality main mailboxes that are accessible through a corresponding port without using the common message input/output line; and

performing a control so that a message writing operation through a predetermined port of the at least two ports is performed on only at least one mailbox corresponding to the predetermined port and the written messages are serially transmitted through the common message input/output line and written to the at least one local mailbox corresponding to the predetermined port, and a message reading operation through the predetermined port is performed on some local mailboxes, having messages to the predetermined port, among the local mailboxes corresponding to the other ports.

28. A semiconductor memory device, comprising:

a first local mailbox block having a plurality of local mailboxes;

a first main mailbox block having a plurality of first main mailboxes;

a first common message input/output line interposed between the first local mailbox block and the first main mailbox block; and

a mailbox sub decoder to selectively couple any one of the plurality of first local mailboxes and any one of the plurality of first main mailboxes to the first common message input/output line.

29. The semiconductor memory device of claim 28, further comprising:

a second local mailbox block having a plurality of second local mailboxes;

a second main mailbox block having a plurality of second main mailboxes;

a second common message input/output line interposed between the second local mailbox block and the second main mailbox block;

wherein the mailbox sub decoder selectively couples any one of the plurality of the second local mailboxes and any one of the plurality of the second main mailboxes to the second common message input/output line.

30. A computer-readable recording medium having embodied thereon a computer program to execute a method of controlling an access to a plurality of mailboxes in a semiconductor memory device having a shared memory area accessed through a plurality of ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device and adapted to perform a message communication between the plurality of ports, wherein the method comprises:

preparing pairs of main and local mailboxes provided in one-to-one correspondence with the plurality of ports, each local mailbox block including a plurality of local mailboxes that are accessible through a data access path for the shared memory area serving as a shared path, and each main mailbox block including a plurality of main mailboxes that are accessible without using the shared path; and

performing a control so that a predetermined port of the plurality of ports has an access right to the shared memory area, a message writing operation on all of main and local mailboxes corresponding to the predetermined port is performed and a message reading operation on some main mailboxes, having messages to the predetermined port, among the main mailboxes corresponding to the other ports is performed, and so that when the predetermined port does not have the access right to the shared memory area, a message writing operation on the main mailboxes corresponding to the predetermined port and a message reading operation on some local mailboxes, having messages to the predetermined ports, among the local mailboxes corresponding to the other ports are performed.