Translated memory protection apparatus for an advanced microprocessor
First Claim
Patent Images
1. A system comprising:
- means for providing an indication whether a first memory address to be written stores a target instruction for a first instruction set architecture which has been translated to at least one host instruction for a second instruction set architecture, the at least one host instruction stored at a second memory address, the means for providing comprising;
a look-aside buffer including a plurality of storage locations for virtual addresses and associated physical addresses including a first storage location for the first memory address, anda storage position corresponding to the first storage location for storing the indication; and
means for responding to the indication and for assuring that the at least one host instruction will not be utilized once the first memory address has been written, in which case the means for responding removes the at least one host instruction from the second memory address.
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Abstract
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
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Citations
26 Claims
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1. A system comprising:
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means for providing an indication whether a first memory address to be written stores a target instruction for a first instruction set architecture which has been translated to at least one host instruction for a second instruction set architecture, the at least one host instruction stored at a second memory address, the means for providing comprising; a look-aside buffer including a plurality of storage locations for virtual addresses and associated physical addresses including a first storage location for the first memory address, and a storage position corresponding to the first storage location for storing the indication; and means for responding to the indication and for assuring that the at least one host instruction will not be utilized once the first memory address has been written, in which case the means for responding removes the at least one host instruction from the second memory address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory controller comprising:
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an address translation buffer including a plurality of storage locations in which recently accessed virtual addresses are to be recorded and in which physical addresses represented by the virtual addresses are to be recorded, each of the storage locations including means for indicating whether a physical address stores an instruction of a target instruction set which has been translated to an instruction of a host instruction set for execution by a computer system including a host processor, the instruction of the host instruction set for execution by the memory controller; and means for detecting an indication in a storage location to prevent a write access of the physical address and for indicating a subsequent operation before accessing the physical address, the means for detecting comprising; means for generating an exception in response to the detection of the indication; and means for responding to the exception to indicate the subsequent operation to be taken with respect to the instruction of a host instruction set before accessing the physical address. - View Dependent Claims (10, 11, 12, 13)
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14. A computer-implemented method comprising:
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checking a storage position for an indication whether a first memory address to be written stores a target instruction for a first instruction set architecture that has been translated to a host instruction for a second instruction set architecture, wherein the host instruction is executable by a host processor and is stored at a second memory address; and preventing utilization of the host instruction subsequent to a write to the first memory address that overwrites the target instruction. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A computer system comprising:
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a memory; and a microprocessor coupled to the memory, the microprocessor comprising a look-aside buffer comprising a plurality of storage locations for virtual addresses and associated physical addresses including a first storage location for a first memory address;
wherein the look-aside buffer comprises a configuration to indicate whether a first memory address to be written stores a target instruction for a first instruction set architecture that has been translated to a host instruction for a second instruction set architecture and that is stored at a second memory address, the host instruction for execution by the microprocessor; and
wherein, in response to an indication that the first memory address to be written stores a target instruction that has been translated to a host instruction, the host instruction will not be utilized once the target instruction at the first memory address has been overwritten. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification