Method and apparatus for using port communications to switch processor modes

• US 7,840,826 B2
• Filed: 05/31/2007
• Issued: 11/23/2010
• Est. Priority Date: 05/31/2007
• Status: Expired due to Fees

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Goff, Lonnie C.
• Primary Examiner(s): Patel; Nitin C
• Application Number:
  US11/809,197
• Publication Number:
  US 20080301482A1
• Time in Patent Office: 1,272 Days
• Field of Search: 713/323, 713/300, 713/320, 712/20
• US Class Current: 713/323
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.

Claims

1. A computer array comprising:

a plurality of processors; and

wherein

each processor is connected to at least two adjoining processors by a plurality of links, each said link being connected to only two of said processors;

said plurality of processors includes

a plurality of edge processors located at the edge of said array, each said edge processor having three links connecting said edge processor to three adjacent processors,

four corner processors, each said corner processor located at a corner of said array and having two of said links connecting said corner processor to two of said edge processors, and

a plurality of hybrid processors, each of said hybrid processors connected by four links to four processors, the link of said edge processor not connected to another one of said edge processors or one of said corner processors being connected to a single said hybrid processor;

said hybrid processors selectively switch between a rest mode, a routing mode, and a processing mode; and

when one of said hybrid processors receives an instruction on one of said links connected to said one of said hybrid processors, said one of said hybrid processors switches between said rest mode and at least one of said routing mode and said processing mode.

2. A computer array as in claim 1, wherein said link includes a plurality of data lines.

3. A computer array as in claim 2, wherein said link further includes a plurality of control lines.

4. A computer array as in claim 3, wherein said control lines are unidirectional.

5. A computer array as in claim 1, wherein at least one of said corner processors of said array includes an interface to couple said at least one corner processor to an external device selected from the group of memory, input devices, display devices and processing devices.

6. A computer array as in claim 1, wherein at least one of said edge processors of said array includes an interface to couple said at least one edge processor to an external device selected from the group of memory, input devices, display devices and processing devices.

7. A computer array as in claim 1, wherein:

each of said links includes a data line and a control line; and

said instruction is a digital word passed over said data line.

8. A computer array as in claim 7, wherein said digital word is a routing word that causes said one of said hybrid processors to switch into said routing mode.

9. A computer array as in claim 7, wherein said digital word is a processing word that causes said one of said hybrid processors to switch into said processing mode.

10. A computer array as in claim 1, wherein:

when, prior to completing a processing task in said processing mode, said one of said hybrid processors receives a subsequent instruction associated with a routing task on one of said links connected to said one of said hybrid processors, said one of said hybrid processors switches from said processing mode to said routing mode to perform said routing task;

said one of said hybrid processors switches back to said processing mode following completion of said routing task to continue said processing task; and

said one of said hybrid processor switches to said rest mode following completion of said processing task.

11. A computer array as in claim 1, wherein:

when said instruction has a processing format, said one of said hybrid processors switches into said processing mode; and

when said instruction has a routing format, said one of said hybrid processors switches into said routing mode.

12. A computer array as in claim 11, wherein:

said instruction includes a plurality of bits;

said instruction has said processing format when each bit in said instruction has the same value; and

said instruction has said routing format when at least two of said bits in said instruction have different values.

13. A computer array as in claims 11, wherein:

said routing format includes a plurality of information fields;

a first information field indicates the amount of data to be routed; and

a second information field contains information specific to an external device.

14. A processor for use in a computer array, said processor comprising:

a central processing unit coupled to at least two links, each of said links connecting said processor to an immediately adjacent processor; and

a memory unit connected to said central processing unit; and

wherein

said central processing unit has three modes including an idle mode for conserving power, a routing mode for performing routing tasks, and a processing mode for performing processing tasks; and

receipt of an instruction on either of said links causes said central processing unit to shift from said idle mode to at least one of said routing mode and said processing mode.

15. A processor for use in a computer array as in claim 14, wherein said central processing unit is coupled to at least two additional links for connecting said processor to two additional immediately adjacent processors for a total of four links for connecting to four immediately adjacent processors.

16. A processor for use in a computer array as in claim 15, wherein said memory unit includes a ROM memory and a RAM memory.

17. A processor for use in a computer array as in claim 15, wherein:

each of said links includes a data line and a control line; and

said instruction is a digital word passed over said data line.

18. A processor for use in a computer array as in claim 17, wherein said control line is unidirectional.

19. A processor for use in a computer array as in claim 14, wherein said central processing unit shifts from said idle mode to said routing mode upon receipt of a routing connection word and stays in said routing mode until said routing task is completed, and, then returns to said idle mode.

20. A processor for use in a computer array as in claim 14, wherein said central processing unit shifts from said idle mode to said processing mode upon receipt of a processing command word, and, stays in said processing mode until said processing task is completed, and, then returns to said idle mode.

21. A processor for use in a computer array as in claim 20, wherein said central processing unit shifts from said idle mode to said routing mode upon receipt of a routing connection word, and, stays in said routing mode until said routing task is completed, and, then returns to said idle mode.

22. A processor for use in a computer array as in claim 14, wherein:

when said central processing unit is in said processing mode and prior to completion of a processing task, receipt of a subsequent instruction associated with a routing task on either of said links causes said central processing unit to shift from said processing mode to said routing mode to perform said routing task;

said central processing unit shifts back to said processing mode following completion of said subsequent routing task to continue said processing task; and

said central processing unit shifts to said rest mode following completion of said processing task.

23. A processor for use in a computer array as in claim 14, wherein:

when said instruction has a processing format, said central processing unit shifts into said processing mode; and

when said instruction has a routing format, said central processing unit shifts into said routing mode.

24. A processor for use in a computer array as in claim 23, wherein:

said instruction includes a plurality of bits;

said instruction has said processing format when each bit in said instruction has the same value; and

said instruction has said routing format when at least two of said bits in said instruction have different values.

25. A processor for use in a computer array as in claims 23, wherein:

said routing format includes a plurality of information fields;

a first information field indicates the amount of data to be routed; and

a second information field contains information specific to an external device.

26. A method for operating a multi processor array, said method comprising:

designating some of the processors in said array as multimode processors having at least an idle mode for conserving power, a routing mode for performing a routing task, and a processing mode performing a processing task;

switching one of said multimode processors from said idle mode into at least one of said processing mode and said routing mode upon receipt of a command word with said one of said multimode processors;

performing one of said routing task and said processing task with said one of said multimode processors upon receipt of said command word; and

switching said one of said multimode processors back to said idle mode upon completion of said performed task.

27. A method for operating a multi processor array as in claim 26, wherein:

said command word defines a routing word indicative of said routing task;

said one of said multimode processors switches into said routing mode upon receipt of said routing word;

said one of said multimode processors performs said routing task; and

said one of said multimode processor returns to said idle mode upon completion of said routing task.

28. A method for operating a multi processor array as in claim 26, further comprising:

switching said one of said multimode processors from said idle mode into said processing mode to perform said processing task upon receipt of said command word;

switching said one of said multimode processors from said processing mode into said routing mode prior to completing said processing task, said switching to said routing mode occurring responsive to said one of said multimode processors receiving a subsequent command word associated with a subsequent routing task;

performing said subsequent routing task with said one of said multimode processors;

switching said one of said multimode processors back to said processing mode following completion of said subsequent routing task;

completing said processing task with said one of said multimode processors; and

switching said one of said multimode processors into said idle mode upon completion of said processing task.

29. A method for operating a multi-processor array as in claim 26, wherein:

said one of said multimode processors switches into said processing mode when said command word has a processing format; and

said one of said multimode processors switches into said routing mode when said command word has a routing format.

30. A method for operating a multi processor array as in claim 29, wherein:

said command word includes a plurality of bits;

said command word has said processing format when each bit in said command word has the same value; and

said command word has said routing format when at least two of said bits in said command word have different values.

31. A method for operating a multi processor array as in claims 29, wherein:

said routing format includes a plurality of information fields;

a first information field indicates the amount of data to be routed; and

a second information field contains information specific to an external device.