Enhanced diagnosis with limited failure cycles

• US 7,840,862 B2
• Filed: 08/25/2006
• Issued: 11/23/2010
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Huang, Yu, Rajski, Janusz, Cheng, Wu-Tung, Klingenberg, Randy, Tamarapalli, Nagesh
• Primary Examiner(s): Tabone, Jr.; John J
• Application Number:
  US11/510,079
• Publication Number:
  US 20070220381A1
• Time in Patent Office: 1,551 Days
• Field of Search: 714/726, 714/729, 714/742
• US Class Current: 714/726
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Claims

1. A method for diagnosing defects in a circuit, the method comprising:

receiving failure log data from a test of the circuit;

identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains or observed at one or more primary outputs after application of a test pattern during the test;

applying a per-pin based diagnosis technique to the truncated failure data to identify one or more fault candidates in the circuit; and

storing a list of the one or more fault candidates.

2. The method of claim 1, wherein the fault candidate is a faulty scan cell candidate.

3. The method of claim 1, wherein the fault candidate is a logic fault candidate.

4. The method of claim 1, wherein applying the per-pin based diagnosis technique further comprises:

identifying a last observed failure cell of the scan chains or a last observed failure cycle of the primary outputs from the truncated failure data; and

masking, during simulations performed as part of the per-pin based diagnosis technique, one or more scan cells of the one or more scan chains after the last observed failure cell or one or more cycles from the one or more primary outputs after the last observed failure cycle.

5. The method of claim 4, wherein applying the per-pin based diagnosis technique further comprises identifying from the failure log data a fault type, and wherein masking comprises masking the one or more scan cells or primary outputs after the last observed failure cell or last observed failure cycle.

6. The method of claim 5, wherein one or more fault types are identified in two or more scan chains or in two or more system logic sections.

7. The method of claim 1, wherein the failure log data indicates a last observed failure cell for the one or more scan chains, wherein the scan chains comprise a last scan cell, and wherein applying the per-pin based diagnosis technique comprises masking one or more scan cells of the scan chains between the last observed failure cell and the last scan cell during simulations performed as part of the per-pin based diagnosis technique.

8. The method of claim 1, wherein applying the per-pin based diagnosis technique further comprises determining a fault range based at least in part on a last-logged failure cycle in the truncated failure data.

9. The method of claim 8, wherein determining the fault range comprises loading the one or more scan chains with at least some masked values during simulations performed as part of the per-pin based diagnosis technique.

10. The method of claim 8, further comprising injecting faults into one or more cells of the one or more scan chains during simulations performed as part of the per-pin based diagnosis technique.

11. The method of claim 1, wherein the test of the circuit comprises loading test patterns into the one or more scan chains and applying the test patterns to one or more system logic sections, the test patterns being arranged by a pattern ordering method that orders the test patterns based at least in part on one or more diagnostic metrics of the test patterns.

12. The method of claim 11, wherein the pattern ordering method is applied before the one or more fault candidates are identified.

13. The method of claim 11, wherein the pattern ordering method is applied after a faulty scan chain is identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of the faulty scan chain.

14. The method of claim 11, wherein the pattern ordering method is applied after one or more faulty scan cells or primary outputs are identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of logic fault candidates that explain the one or more faulty scan cells or primary outputs.

15. The method of claim 1, wherein the failure log data comprises a number of failure cycles recorded for a respective test pattern applied during testing, the number of failure cycles being determined at least in part by user input.

16. The method of claim 1, wherein the failure log data is associated with compressed test responses captured during the test.

17. The method of claim 1, wherein the truncated failure data comprises incomplete failure log data.

18. The method of claim 1, wherein the applying the per-pin based diagnosis technique comprises performing one or more circuit simulations based at least in part on the truncated failure data.

19. An electronic design automation system comprising:

means for receiving failure log data from a test of the circuit;

means for identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains or observed at one or more primary outputs after application of a test pattern during the test;

means for applying a per-pin based diagnosis technique to the truncated failure data to identify one or more fault candidates in the circuit; and

means for storing a list of the one or more fault candidates.

20. One or more computer-readable media containing instructions which, when executed by a computer, cause the computer to perform a method, the method comprising:

receiving failure log data from a test of a circuit;

identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains or observed at one or more primary outputs after application of a test pattern during the test;

applying a per-pin based diagnosis technique to the truncated failure data to identify one or more fault candidates in the circuit; and

storing a list of the one or more fault candidates.

21. The one or more computer-readable media of claim 20, wherein the fault candidate is a faulty scan cell candidate.

22. The one or more computer-readable media of claim 20, wherein the fault candidate is a logic fault candidate.

23. The one or more computer-readable media of claim 20, wherein applying the per-pin based diagnosis technique further comprises:

identifying a last observed failure cell of the scan chains or a last observed failure cycle of the primary outputs from the truncated failure data; and

masking, during simulations performed as part of the per-pin based diagnosis technique, one or more scan cells of the one or more scan chains after the last observed failure cell or one or more cycles from the one or more primary outputs after the last observed failure cycle.

24. The one or more computer-readable media of claim 23, wherein applying the per-pin based diagnosis technique further comprises identifying from the failure log data a fault type, and wherein masking comprises masking the one or more scan cells or primary outputs after the last observed failure cell or last observed failure cycle.

25. The one or more computer-readable media of claim 24, wherein one or more fault types are identified in two or more scan chains or in two or more system logic sections.

26. The one or more computer-readable media of claim 20, wherein the failure log data indicates a last observed failure cell for the one or more scan chains, wherein the scan chains comprise a last scan cell, and wherein applying the per-pin based diagnosis technique comprises masking one or more scan cells of the scan chains between the last observed failure cell and the last scan cell during simulations performed as part of the per-pin based diagnosis technique.

27. The one or more computer-readable media of claim 20, wherein applying the per-pin based diagnosis technique further comprises determining a fault range based at least in part on a last-logged failure cycle in the truncated failure data.

28. The one or more computer-readable media of claim 27, wherein determining the fault range comprises loading the one or more scan chains with at least some masked values during simulations performed as part of the per-pin based diagnosis technique.

29. The one or more computer-readable media of claim 27, wherein the method further comprises injecting faults into one or more cells of the one or more scan chains during simulations performed as part of the per-pin based diagnosis technique.

30. The one or more computer-readable media of claim 20, wherein the test of the circuit comprises loading test patterns into the one or more scan chains and applying the test patterns to one or more system logic sections, the test patterns being arranged by a pattern ordering method that orders the test patterns based at least in part on one or more diagnostic metrics of the test patterns.

31. The one or more computer-readable media of claim 30, wherein the pattern ordering method is applied before the one or more fault candidates are identified.

32. The one or more computer-readable media of claim 30, wherein the pattern ordering method is applied after a faulty scan chain is identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of the faulty scan chain.

33. The one or more computer-readable media of claim 30, wherein the pattern ordering method is applied after one or more faulty scan cells or primary outputs are identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of logic fault candidates that explain the one or more faulty scan cells or primary outputs.

34. The one or more computer-readable media of claim 20, the failure log data comprising a number of failure cycles recorded for a respective test pattern applied during testing, the number of failure cycles being determined at least in part by user input.

35. The one or more computer-readable media of claim 20, wherein the failure log data is associated with compressed test responses captured during the test.

36. The one or more computer-readable media of claim 20, wherein the truncated failure data comprises incomplete failure log data.

37. The one or more computer-readable media of claim 20, wherein the applying the per-pin based diagnosis technique comprises performing one or more circuit simulations based at least in part on the truncated failure data.

38. A computer-readable medium having encoded thereon a list of one or more fault candidates determined according to a method, the method comprising:

receiving failure log data from a test of a circuit;

identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains or observed at one or more primary outputs after application of a test pattern during the test;

applying a per-pin based diagnosis technique to the truncated failure data to identify the one or more fault candidates in the circuit; and

storing the list of the one or more fault candidates in the computer-readable medium.

39. A method for diagnosing defects in one or more scan chains of a circuit, the scan chains respectively comprising one or more scan cells, the method comprising:

receiving failure log data from a test of the circuit;

identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains after application of a test pattern during test;

applying a per-pin based diagnosis technique to the truncated failure data to identify one or more faulty scan cell candidates in the scan cell chains; and

storing a list of the one or more faulty scan cell candidates.