Multi-chip packaging using an interposer with through-vias

• US 7,841,080 B2
• Filed: 05/30/2007
• Issued: 11/30/2010
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Mancera, Raul, Tomita, Yoshihiro, Hwang, Chi-won, Muthukumar, Sriram
• Primary Examiner(s): Nguyen; Donghai D.
• Application Number:
  US11/755,735
• Publication Number:
  US 20080295325A1
• Time in Patent Office: 1,280 Days
• Field of Search: 29830-832, 298/40, 298/46, 298/52, 298/53, 174/260, 174/262, 438/108, 438/459, 438/667, 438/672, 257/476
• US Class Current: 29/851
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49163 with sintering of base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.

Claims

1. A method comprising:

forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body;

forming an electrically insulating layer on the sidewalls in the vias and on an upper surface of the body;

forming an electrically conductive layer on the electrically insulating layer in the vias and on the upper surface, the electrically conductive layer defining first medal pads on the upper surface and second medal pads in contact with first medal pads, second medal pads having a denser pitch than the first metal pads;

forming a dielectric layer between adjacent first metal pads and forming a dielectric layer between adjacent second metal pads;

coupling a plurality of electronic elements to the second metal pads;

after the coupling the electronic elements, thinning the body through a lower surface and exposing the electrically insulating layer in the vias;

removing a portion of the electrically insulating layer in the vias; and

coupling the body to a substrate, wherein the body is positioned between the elements and the substrate.

2. The method of claim 1, wherein the body comprises silicon, wherein the electronic elements comprise silicon die structures, and wherein the electronic elements are flip-chip coupled to a plurality of the second metal pads.

3. The method of claim 1, further comprising forming at least one of an interfacial layer and a seed layer between the electrically insulating layer and the electrically conductive layer.

4. The method of claim 1, wherein an interfacial layer is formed directly on the electrically insulating layer, a metal seed layer is formed directly on the interfacial layer, and the electrically conductive layer is formed directly on the metal seed layer using a plating method.

5. The method of claim 1, wherein the body comprises a wafer, and after the coupling the electronic elements and the thinning the body, dicing the wafer into a plurality of interposers.

6. The method of claim 1, further comprising coupling a lid to the substrate after the coupling the exposed electrically conductive layer to the substrate, wherein the lid is positioned to cover the electronic elements.

7. The method of claim 1, wherein the electronic elements include at least one of a central processing unit, a plurality of memory elements, and an integrated silicon voltage regulator, wherein the central processing unit is centrally positioned with respect to the plurality of memory elements and the integrated silicon voltage regulator.

8. The method of claim 1, wherein the electronic elements include a central processing unit and a plurality of memory elements.