Masking process for simultaneously patterning separate regions

• US 7,842,558 B2
• Filed: 03/02/2006
• Issued: 11/30/2010
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Tran; Tony
• Application Number:
  US11/367,020
• Publication Number:
  US 20070205438A1
• Time in Patent Office: 1,734 Days
• Field of Search: 257/216, 257135-136, 257/242, 257/329, 257/E27.091, 257 27095- 27096, 257/E29.118, 257/E29.274, 257/E29.313, 257/E29.318, 257/E29.262
• US Class Current: 438/135
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Claims

1. A method comprising:

patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask;

providing at least one gate layer in a logic portion of the semiconductor substrate and at least one sacrificial layer in the array portion of the semiconductor substrate;

after patterning the first plurality of semiconductor structures, patterning a plurality of gate structures from the gate layer over the logic portion of the semiconductor substrate using a second photolithographic mask;

patterning the sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask, wherein patterning the plurality of gate structures and patterning the sacrificial layer are performed simultaneously;

using the patterned sacrificial layer to define a hard mask over the array portion of the semiconductor substrate, wherein a hard mask material is deposited between features of the patterned sacrificial layer; and

subsequently removing all of the patterned sacrificial layer.

2. The method of claim 1, wherein the sacrificial layer comprises polycrystalline silicon.

3. The method of claim 1, wherein the first plurality of semiconductor structures are recessed into the semiconductor substrate.

4. The method of claim 1, wherein the first plurality of semiconductor structures are recessed below the plurality of gate structures.

5. The method of claim 1, wherein the first plurality of semiconductor structures are U-shaped transistor structures.

6. The method of claim 1, wherein the plurality of gate structures form part of planar transistor structures.

7. The method of claim 1, further comprising performing an ion implantation technique to dope selected portions of the first semiconductor structures.

8. The method of claim 1, wherein the plurality of gate structures comprises a polycrystalline silicon region.

9. The method of claim 8, wherein the plurality of gate structures further comprises a gate dielectric layer positioned between the logic portion of the semiconductor substrate and the polycrystalline silicon region.

10. The method of claim 1, wherein the plurality of gate structures comprises a silicide region.

11. The method of claim 1, wherein patterning the first plurality of semiconductor structures over the array portion of the semiconductor substrate comprises:

forming a plurality of elongate shallow trenches; and

forming a plurality of elongate deep trenches positioned substantially parallel to the plurality of elongate shallow trenches.

12. The method of claim 11, wherein forming the plurality of elongate shallow trenches and the plurality of elongate deep trenches comprises performing a pitch multiplication process.

13. The method of claim 11, wherein patterning the first plurality of semiconductor structures over the array portion of the semiconductor substrate further comprises filling the elongate shallow trenches and the elongate deep trenches with an oxide material.

14. The method of claim 1, wherein the semiconductor substrate comprises single crystal silicon.

15. The method of claim 1, further comprising depositing a conformal insulating layer over the second plurality of semiconductor structures.

16. The method of claim 15, wherein:

patterning the sacrificial layer comprises forming a plurality of gaps in the sacrificial layer, the gaps having a gap spacing; and

the conformal insulating layer has a thickness that is at least half the gap spacing.

17. The method of claim 15, further comprising etching the conformal insulating layer from horizontal surfaces in the array and logic portions of the semiconductor substrate.

18. The method of claim 17, wherein etching the conformal insulating layer forms a plurality of sidewall spacers adjacent the second plurality of semiconductor structures over the logic portion of the semiconductor substrate.

19. The method of claim 15, wherein the conformal insulating layer comprises silicon nitride.

20. The method of claim 1, wherein subsequently removing all of the patterned sacrificial layer is conducted after defining the hard mask.

21. The method of claim 20, further comprising etching a plurality of trenches through the hard mask and into the array portion of the semiconductor substrate after removing the patterned sacrificial layer.

22. The method of claim 21, further comprising forming a plurality of elongate sidewall spacers adjacent to vertical sidewalls of the plurality of trenches etched into the array portion of the semiconductor substrate.

23. The method of claim 22, wherein the plurality of elongate sidewall spacers comprises a semiconductor material.

24. The method of claim 22, further comprising an oxide layer positioned between the plurality of elongate spacers and the vertical sidewalls of the plurality of trenches etched into the array portion of the semiconductor substrate.

25. The method of claim 1, wherein the gate layer and the sacrificial layer comprise the same conductive layer in the array and logic portions.

26. The method of claim 25, wherein patterning the gate layer and patterning the sacrificial layer comprises masking the gate layer and the sacrificial layer and etching a conductive layer and an underlying dielectric layer.