Method of manufacturing a semiconductor power device

• US 7,842,574 B2
• Filed: 01/08/2008
• Issued: 11/30/2010
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Donato, Caterina, Arena, Giuseppe, Magri, Angelo, Camalleri, Cateno Marco
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Hall; Jessica
• Application Number:
  US11/971,114
• Publication Number:
  US 20080211015A1
• Time in Patent Office: 1,057 Days
• Field of Search: 257/330, 257/E29.133, 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

Claims

1. A process for manufacturing a semiconductor power device, comprising the steps of:

forming a semiconductor body of a first conductivity type and having a top surface;

forming, in said semiconductor body, a trench having side walls and a bottom;

coating said side walls and said bottom of said trench with a first dielectric material layer;

filling said trench with a second dielectric material layer and an auxiliary dielectric material layer;

etching said first, second, and auxiliary dielectric material layers via an etching process wherein, at the end of said etching step, said trench houses, at the bottom, portions of said first, second, and auxiliary dielectric material layers, said portions of the first and second dielectric material layers having a depth that is approximately equal and the auxiliary layer has a forked top profile;

forming a gate-oxide layer on said walls of said trench;

forming a gate region of conductive material within said trench and surrounded by said gate-oxide layer; and

forming, within said semiconductor body, a body region having a second conductivity type and a source region having said first conductivity type,

said first, second, and auxiliary dielectric material layers comprising materials having similar responses to said etching process, and said etching step comprising simultaneously etching said first dielectric material layer, said second dielectric material layer, and said auxiliary dielectric material layer so as to remove a portion of each of said first, second, and auxiliary dielectric material layers in a partial, simultaneous and controlled way within said trench.

2. The process according to claim 1 wherein said etching step comprises removing said first, second, and auxiliary dielectric material layers from said surface and continuing said etching step so as to remove a further portion of said first, second, and auxiliary dielectric material layers.

3. The process according to claim 1 wherein said etching step comprises using a dry etching process.

4. The process according to claim 3 wherein said dry etching process comprises carrying out a plasma etch with a reactive gas.

5. The process according to claim 4 wherein said reactive gas comprises tetrafluoromethane (CF₄)/trifluoromethane (CHF₃)/argon.

6. The process according to claim 1 wherein said first dielectric material layer is silicon dioxide, said second dielectric material layer is TEOS (tetraethylorthosilicate), and said auxiliary dielectric material layer is silicon nitride.

7. The process according claim 1 wherein said step of forming a trench in said semiconductor body is followed by implanting dopant ion species and forming a modified-conductivity region underneath said trench.

8. The process according to claim 1 wherein said step of forming a gate region is followed by forming a metal layer on top of said gate region.

9. The process according to claim 8 wherein the step of forming a metal layer comprises a silicidation step using a metal from the group of cobalt, titanium, and tungsten.

10. The process according to claim 1 wherein said step of forming a source region comprises a blanket implantation of a dopant species.

11. The process according to claim 10 wherein said steps of forming a body region and a source region are followed by the steps of:

depositing an insulating layer on said surface;

forming an opening extending through said insulating layer and said source region and partially into said body region; and

filling said opening with metal.

12. The process according to claim 1 wherein said step of forming a gate region is followed by partially removing said conductive material within said trench and filling said trench with dielectric material.

13. The process according to claim 12 wherein said step of partially removing said conducting material is followed by a step of depositing a gate metallization layer.

14. The process according to claim 1 wherein said second dielectric material layer has a first thickness and said gate-oxide layer has a second thickness smaller than said first thickness.

15. A method, comprising:

forming a trench in a semiconductor body;

coating side walls and a bottom of the trench with a first dielectric material;

forming an oxide layer on the first dielectric material layer;

filling the trench with a second dielectric material; and

removing a portion of the first dielectric material layer, the oxide, and the second dielectric material using an etching process that simultaneously and partially removes the first dielectric material layer, the oxide, and the second dielectric material and forms a forked top profile on the second dielectric material.

16. The method of claim 15, comprising the further steps of:

forming a gate oxide layer on the walls of the trench exposed by the etching process;

filling the trench with a conductive material to form a gate region; and

forming in the semiconductor body a body region and a source region.

17. The method of claim 16 wherein the step of forming a trench in the semiconductor body is followed by implanting dopant ion species to form a modified conductivity region underneath the trench.

18. The method of claim 15 wherein the oxide layer comprises TEOS (tetraethylorthosilicate) and the second dielectric material comprises silicon nitride.

19. The method of claim 15, wherein removing comprises etching the first dielectric material layer, the oxide layer, and the second dielectric material so that the first dielectric material layer and the oxide have a depth that is approximately equal.