Organic inverter including surface-treated layer and method of manufacturing the same

• US 7,842,952 B2
• Filed: 10/31/2007
• Issued: 11/30/2010
• Est. Priority Date: 12/07/2006
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Koo, Jae Bon, Kim, Seong Hyun, Suh, Kyung Soo
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): Sengdara; Vongsavanh
• Application Number:
  US11/931,461
• Publication Number:
  US 20080135947A1
• Time in Patent Office: 1,126 Days
• Field of Search: 257/40, 257/59, 257/72, 257/347, 257/348, 257/350, 257/351, 257/E51.006, 257/E29.117, 257/E29.137, 257/E29.29, 257/E29.291, 257/E29.293, 257/E29.294
• US Class Current: 257/59
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors

Abstract

An organic inverter and a method of manufacturing the same are provided, which regulates threshold voltages depending on positions when an inverter circuit is manufactured on a substrate using an organic semiconductor. To form a depletion load transistor and an enhancement driver transistor at adjacent positions of the same substrate, the surface of the substrate is selectively treated by positions or selectively applied by self-assembly monolayer treatment. Thus, a D-inverter having a combination of a depletion mode and an enhancement mode is more easily realized than a conventional method using a transistor size effect. Also, the D-inverter can be realized even with the same W/L ratio, thereby increasing integration density. That is, the W/L ratio does not need to be increased to manufacture a depletion load transistor, thereby improving integration density.

Claims

1. An inverter, comprising:

a load transistor including a gate electrode, source and drain electrodes, a load insulating layer formed on the gate electrode, the source electrode being connected to the gate electrode, and an organic semiconductor layer formed on the load insulating layer;

a driver transistor connected to the load transistor and including a gate electrode, source and drain electrodes, a driver insulating layer formed on the gate electrode, and an organic semiconductor layer formed on the load insulating layer, wherein the drain electrode of the driver transistor is directly connected to the gate electrode of the load transistor, and

a surface-treated layer formed on a predetermined insulating layer, the predetermined insulating layer being one of the load insulating layer and the driver insulating layer, such that the driver transistor is a depletion-type transistor and the load transistor is an enhancement-type transistor,

wherein the load transistor and the driver transistor have substantially the same W/L ratio.

2. The inverter according to claim 1, wherein when the predetermined insulating layer is the load insulating layer, the surface-treated layer is a portion of the load insulating layer damaged by UV-ozone treatment, O₂ treatment, or laser irradiation.

3. The inverter according to claim 2, wherein the surface-treated layer formed on the load insulating layer increases the drain current in the load transistor.

4. The inverter according to claim 1, wherein when the predetermined insulating layer is the driver insulating layer, the surface-treated layer is a octadecyltrichlorosilane (OTS) treated surface of the driver insulating layer or a hexamethyldisilazane (HMDS) treated surface of the driver insulating layer.

5. The inverter according to claim 4, wherein the surface-treated layer formed on the driver insulating layer moves the threshold voltage in the direction of a negative gate voltage in the driver transistor such that the driver transistor has a depletion characteristic.

6. The inverter according to claim 1, wherein the source and drain electrodes and the gate electrode are formed of a metallic material, a conductive oxide or a conductive polymer.

7. The inverter according to claim 6, wherein the gate electrode is formed of one selected from a group consisting of Ti, Cu, Cr, AI, Au, Mo, W, ITO, IZO and PEDOT.

8. The inverter according to claim 6, wherein the source and drain electrodes are formed of one selected from a group consisting of Au, Pt, Ni, Pd, ITO, IZO and PEDOT.

9. The inverter according to claim 1, wherein the load transistor is a bottom gate type or a top gate type.

10. The inverter according to claim 1, wherein the driver transistor is a bottom gate type or a top gate type.

11. The inverter according to claim 1, wherein the load transistor and the driver transistor are formed on the same substrate.

12. An inverter, comprising:

a p-type load transistor including a gate electrode, source and drain electrodes, a load insulating layer formed on the gate electrode, the source electrode being connected to the gate electrode, and an organic semiconductor layer formed on the load insulating layer;

a p-type driver transistor connected to the p-type load transistor and including a gate electrode, source and drain electrodes, a driver insulating layer formed on the gate electrode, and an organic semiconductor layer formed on the load insulating layer, wherein the drain electrode of the p-type driver transistor is directly connected to the gate electrode of the p-type load transistor; and

a surface-treated layer formed on a predetermined insulating layer, the predetermined insulating layer being one of the load insulating layer and the driver insulating layer, such that the load transistor is a depletion-type transistor and the driver transistor is an enhancement-type transistor,

wherein the p-type load transistor and the p-type driver transistor have substantially the same W/L ratio.

13. The inverter according to claim 12, wherein when the predetermined insulating layer is the load insulating layer, the surface-treated layer is a portion of the load insulating layer damaged by UV-ozone treatment, O₂ treatment, or laser irradiation.

14. The inverter according to claim 12, wherein when the predetermined insulating layer is the driver insulating layer, the surface-treated layer is a octadecyltrichlorosilane (OTS) treated surface of the driver insulating layer or a hexamethyldisilazane (HMDS) treated surface of the driver insulating layer.

15. The inverter according to claim 12, wherein the source and drain electrodes and the gate electrode are formed of a metallic material, a conductive oxide or a conductive polymer.

16. The inverter according to claim 15, wherein the gate electrode is formed of one selected from a group consisting of Ti, Cu, Cr, AI, Au, Mo, W, ITO, IZO and PEDOT, and wherein the source and drain electrodes are formed of one selected from a group consisting of Au, Pt, Ni, Pd, ITO, IZO and PEDOT.