Nonvolatile semiconductor memory device having floating gate that includes two layers

• US 7,842,992 B2
• Filed: 03/20/2007
• Issued: 11/30/2010
• Est. Priority Date: 03/31/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Takano, Tamae, Yamazaki, Shunpei, Asami, Yoshinobu
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Bernstein; Allison P
• Application Number:
  US11/723,506
• Publication Number:
  US 20070228448A1
• Time in Patent Office: 1,351 Days
• Field of Search: 257314-316, 257/324, 257/E29.3, 257/E21.422
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.

Claims

1. A nonvolatile semiconductor memory device comprising:

a substrate;

a base insulating layer over the substrate;

a semiconductor layer over the base insulating layer, the semiconductor layer including a channel forming region between a first impurity region and a second impurity region which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in direct contact with the first insulating layer and a second layer formed over the first layer,

wherein the first layer comprises germanium or a germanium compound, and

wherein the second layer is formed of a material selected from the group consisting of a metal, an alloy, and a metal compound which is different from the germanium or the germanium compound.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the germanium compound is germanium oxide or germanium nitride.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer is an island-like semiconductor layer formed over the base insulating layer.

5. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the floating gates and the control gates are arranged over the semiconductor layer, each control gate being stacked over the floating gate.

6. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

7. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

8. The nonvolatile semiconductor memory device according to claim 1,

wherein the semiconductor layer includes a third impurity region having a conductivity type which is different from a conductivity type of the first impurity region and the second impurity region,

wherein the third impurity region is provided in an edge portion of the semiconductor layer in a channel width direction, and

wherein an edge of the floating gate in the channel width direction is provided over the third impurity region.

9. The nonvolatile semiconductor memory device according to claim 8, wherein the third impurity region extends in a channel length direction.

10. The nonvolatile semiconductor memory device according to claim 8, wherein the semiconductor layer includes a fourth impurity region having a same conductivity type as the conductivity type of the third impurity region, and the channel forming region is provided between the third impurity region and the fourth impurity region.

11. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has a same conductivity type as a conductivity type of the first impurity region and the second impurity region.

12. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer contains at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

13. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer contains at least one of tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, tantalum oxide, titanium oxide, and molybdenum oxide.

14. The nonvolatile semiconductor memory device according to claim 1, wherein the first layer comprises germanium or a germanium compound and has a thickness of 1 nm to 20 nm.

15. The nonvolatile semiconductor memory device according to claim 1, wherein the control gate includes a first conductive layer and a second conductive layer over the first conductive layer, and an edge of the first conductive layer in a channel length direction extends beyond an edge of the second conductive layer.

16. A nonvolatile semiconductor memory device comprising:

a substrate;

a base insulating layer over the substrate;

a semiconductor layer over the base insulating layer, the semiconductor layer including a channel forming region between a first impurity region and a second impurity region which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in direct contact with the first insulating layer and a second layer formed over the first layer,

wherein the first layer comprises germanium or a germanium compound,

wherein the second layer is formed of a material selected from the group consisting of a metal, an alloy, and a metal compound which is different from the germanium and the germanium compound, and

wherein the germanium compound is germanium oxide or germanium nitride.

17. The nonvolatile semiconductor memory device according to claim 16, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.

18. The nonvolatile semiconductor memory device according to claim 16, wherein the semiconductor layer is an island-like semiconductor layer formed over the base insulating layer.

19. The nonvolatile semiconductor memory device according to claim 16, wherein a plurality of the floating gates and the control gates are arranged over the semiconductor layer, each control gate being stacked over the floating gate.

20. The nonvolatile semiconductor memory device according to claim 16, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

21. The nonvolatile semiconductor memory device according to claim 16,

wherein the semiconductor layer includes a third impurity region having a conductivity type which is different from a conductivity type of the first impurity region and the second impurity region,

wherein the third impurity region is provided in an edge portion of the semiconductor layer in a channel width direction, and

wherein an edge of the floating gate in the channel width direction is provided over the third impurity region.

22. The nonvolatile semiconductor memory device according to claim 21, wherein the third impurity region extends in a channel length direction.

23. The nonvolatile semiconductor memory device according to claim 21, wherein the semiconductor layer includes a fourth impurity region having a same conductivity type as the conductivity type of the third impurity region, and the channel forming region is provided between the third impurity region and the fourth impurity region.

24. The nonvolatile semiconductor memory device according to claim 16, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has a same conductivity type as a conductivity type of the first impurity region and the second impurity region.

25. The nonvolatile semiconductor memory device according to claim 16, wherein the second layer contains at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

26. The nonvolatile semiconductor memory device according to claim 16, wherein the second layer contains at least one of tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, tantalum oxide, titanium oxide, and molybdenum oxide.

27. The nonvolatile semiconductor memory device according to claim 16, wherein the first layer comprises germanium or a germanium compound and has a thickness of 1 nm to 20 nm.

28. The nonvolatile semiconductor memory device according to claim 16, wherein the control gate includes a first conductive layer and a second conductive layer over the first conductive layer, and an edge of the first conductive layer in a channel length direction extends beyond an edge of the second conductive layer.

29. A nonvolatile semiconductor memory device comprising:

a substrate;

a base insulating layer over the substrate;

an island-like semiconductor layer over the base insulating layer, the island-like semiconductor layer including a channel forming region between a first impurity region and a second impurity region which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in direct contact with the first insulating layer and a second layer formed over the first layer,

wherein the first layer comprises germanium or a germanium compound,

wherein the second layer is formed of a material selected from the group consisting of a metal, an alloy, and a metal compound which is different from the germanium and the germanium compound, and

wherein a plurality of the floating gates and the control gates are arranged over the island-like semiconductor layer, each control gate being stacked over the floating gate.

30. The nonvolatile semiconductor memory device according to claim 29, wherein the germanium compound is germanium oxide or germanium nitride.

31. The nonvolatile semiconductor memory device according to claim 29, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.

32. The nonvolatile semiconductor memory device according to claim 29, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

33. The nonvolatile semiconductor memory device according to claim 29,

wherein the island-like semiconductor layer includes a third impurity region having a conductivity type which is different from a conductivity type of the first impurity region and the second impurity region,

wherein the third impurity region is provided in an edge portion of the island-like semiconductor layer in a channel width direction, and

wherein an edge of the floating gate in the channel width direction is provided over the third impurity region.

34. The nonvolatile semiconductor memory device according to claim 33, wherein the third impurity region extends in a channel length direction.

35. The nonvolatile semiconductor memory device according to claim 33, wherein the island-like semiconductor layer includes a fourth impurity region having a same conductivity type as the conductivity type of the third impurity region, and the channel forming region is provided between the third impurity region and the fourth impurity region.

36. The nonvolatile semiconductor memory device according to claim 29, wherein the island-like semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has a same conductivity type as a conductivity type of the first impurity region and the second impurity region.

37. The nonvolatile semiconductor memory device according to claim 29, wherein the second layer contains at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

38. The nonvolatile semiconductor memory device according to claim 29, wherein the second layer contains at least one of tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, tantalum oxide, titanium oxide, and molybdenum oxide.

39. The nonvolatile semiconductor memory device according to claim 29, wherein the first layer comprises germanium or a germanium compound and has a thickness of 1 nm to 20 nm.

40. The nonvolatile semiconductor memory device according to claim 29, wherein the control gate includes a first conductive layer and a second conductive layer over the first conductive layer, and an edge of the first conductive layer in a channel length direction extends beyond an edge of the second conductive layer.