Method and structure for improving device performance variation in dual stress liner technology

• US 7,843,024 B2
• Filed: 12/04/2008
• Issued: 11/30/2010
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Greene, Brian J., Chidambarrao, Dureseti
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US12/328,358
• Publication Number:
  US 20090079011A1
• Time in Patent Office: 726 Days
• Field of Search: 438/53, 438/902, 438/158, 438/183, 257/254, 257/418, 257/E21.453
• US Class Current: 257/418
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate having at least one dummy gate region in proximity to at least one FET; and

a tensile stress liner or a compressive stress liner located on said substrate, wherein said stress liner covers the at least one FET and is present in part over said at least one dummy gate region such that an etched edge of the stress liner lands on top of said at least one dummy gate region.

2. A semiconductor structure comprising:

a semiconductor substrate having at least one dummy gate region in proximity to at least one nFET; and

a tensile stress liner and a compressive stress liner located on said substrate, wherein said tensile stress liner covers the at least one nFET and is present in part over said at least one dummy gate region such that an boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

3. The semiconductor structure of claim 2 wherein stress liners overlap each other atop the dummy gate region.

4. The semiconductor structure of claim 2 wherein stress liners abut each other atop the dummy gate region or a space is located between the two stress liners atop the dummy gate region.

5. The semiconductor structure of claim 2 wherein said dummy gate region is located atop an isolation region that is located within or on said semiconductor substrate.

6. A semiconductor structure comprising:

a semiconductor substrate having at least one dummy gate region in proximity to at least one pFET; and

a tensile stress liner and a compressive stress liner located on said substrate, wherein said compressive stress liner covers the at least one pFET and is present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

7. The semiconductor structure of claim 6 wherein stress liners overlap each other atop the dummy gate region.

8. The semiconductor structure of claim 6 wherein stress liners abut each other atop the dummy gate region or a space is located between the two stress liners atop the dummy gate region.

9. The semiconductor structure of claim 6 wherein said dummy gate region is located atop an isolation region that is located within or on said semiconductor substrate.

10. A semiconductor structure comprising:

a semiconductor substrate having at least one dummy gate region in proximity to at least one active gate region; and

a tensile stress liner and a compressive stress liner located on said substrate, wherein said tensile stress liner and said compressive stress liner are present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

11. The semiconductor structure of claim 10 wherein said semiconductor substrate comprises a Si-containing substrate having a single crystal orientation.

12. The semiconductor structure of claim 10 wherein said semiconductor substrate is a hybrid substrate including surface regions of different crystal orientations, wherein each active gate region is disposed on a crystal orientation that provides optimal device performance.

13. The semiconductor structure of claim 10 wherein said compressive stress liner covers said at least one active gate region and overlaps a segment of the tensile stress liner atop said dummy gate region.

14. The semiconductor structure of claim 13 wherein said at least one active gate region is a pFET.

15. The semiconductor structure of claim 10 wherein said tensile stress liner covers said at least one active gate region and overlaps a segment of the compressive stress liner atop said dummy gate region.

16. The semiconductor structure of claim 15 wherein said at least one active gate region is an nFET.

17. The semiconductor structure of claim 10 wherein said stress liners abut each other, over said dummy gate region or a space is present there between.

18. The semiconductor structure of claim 10 wherein said dummy gate region is located atop an isolation region that is located within or on said semiconductor substrate.

19. A method of forming a semiconductor structure comprising:

providing a semiconductor substrate having at least one dummy gate region in proximity to at least one active gate region; and

disposing, in any order, a tensile stress liner and a compressive stress liner on said substrate, wherein said tensile stress liner and said compressive stress liner are present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

20. The method of claim 19 wherein said tensile stress liner is disposed first followed by said compressive stress liner thereby said compressive stress liner covers said at least one active gate region and overlaps a segment of the tensile stress liner atop said dummy gate region.

21. The method of claim 19 wherein said compressive stress liner is disposed first followed by said tensile stress liner thereby said tensile stress liner covers said at least one active gate region and overlaps a segment of the compressive stress liner atop said dummy gate region.

22. The method of claim 19 wherein said disposing comprises deposition, lithography and etching.

23. The method of claim 22 wherein said deposition comprises a chemical vapor deposition process selected from the group consisting of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, and BTBAS-based chemical vapor deposition.

24. The method of claim 19 wherein semiconductor substrate is a hybrid substrate including surface regions of different crystal orientations, wherein each active gate region is disposed on a crystal orientation that provides optimal device performance.

25. The method of claim 19 wherein each dummy gate region comprises a stack including, from bottom to top, a gate dielectric and a gate electrode.

26. The method of claim 19 wherein each active gate region comprises a stack including, from bottom to top, gate dielectric and a gate electrode, a channel region between said stack and adjoining source/drain regions.

27. The method of claim 19 wherein stress liners abut each other atop the dummy gate region or a space is located between the two stress liners atop the dummy gate region.

28. The method of claim 19 wherein said dummy gate region is located atop an isolation region that is located within or on said semiconductor substrate.