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Method and structure for improving device performance variation in dual stress liner technology

  • US 7,843,024 B2
  • Filed: 12/04/2008
  • Issued: 11/30/2010
  • Est. Priority Date: 08/30/2006
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a semiconductor substrate having at least one dummy gate region in proximity to at least one FET; and

    a tensile stress liner or a compressive stress liner located on said substrate, wherein said stress liner covers the at least one FET and is present in part over said at least one dummy gate region such that an etched edge of the stress liner lands on top of said at least one dummy gate region.

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