Integrated circuits

• US 7,843,220 B2
• Filed: 12/22/2006
• Issued: 11/30/2010
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Winblad, Marko, Melakari, Klaus, Kolinummi, Pasi
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/519,725
• Publication Number:
  US 20100097100A1
• Time in Patent Office: 1,439 Days
• Field of Search: None
• US Class Current: 326/62
• CPC Class Codes: H03K 19/0175 Coupling arrangements; Interface arrangements interface arrangements for digital computers G06F3/00, G06F13/00

Abstract

An integrated circuit comprises a processor, a controller and plural terminals. Each terminal constitutes a connection between the integrated circuit and a peripheral device. Each terminal is connected to a logic circuit on the integrated circuit by a respective IO cell in series connection with a respective IO isolation circuit and wherein the controller is operable on power up of the integrated circuit to activate a reset state and to release the reset state prior to releasing IO isolation by one or more of the IO isolation circuits. Each IO isolation circuit may be arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit. The IO isolation circuits may be controllable by software, for instance a driver for a peripheral device connected to the terminal associated with the IO isolation circuit. Plural IO isolation circuits may be connected so as to be commonly controllable by a single control signal from the controller.

Claims

1. An apparatus comprising a processor, a controller and plural terminals, each terminal comprising a connection between the apparatus and a peripheral device,

wherein each terminal interfaces to a logic circuit on the apparatus by a respective input/output IO cell in series connection with a respective IO isolation circuit and wherein the controller is operable on power up of the apparatus to activate a reset state and to release the reset state prior to releasing IO isolation by one or more of the IO isolation circuits.

2. An apparatus as claimed in claim 1, wherein each IO isolation circuit is arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit.

3. An apparatus as claimed in claim 1, wherein the IO isolation circuits are controllable by software.

4. An apparatus as claimed in claim 3, wherein the software is a driver for a peripheral device connected to the terminal associated with the IO isolation circuit.

5. An apparatus as claimed in claim 1, wherein plural IO isolation circuits are connected so as to be commonly controllable by a single control signal from the controller.

6. An apparatus as claimed in claim 1, wherein the IO isolation circuits are powered by an IO cell voltage supply.

7. An apparatus as claimed in claim 1, comprising a respective voltage shifter circuit interposed between each IO cell and the corresponding IO isolation circuit.

8. An apparatus as claimed in claim 1, wherein each IO isolation circuit is interposed between its corresponding IO cell and a respective voltage shifter circuit.

9. An apparatus as claimed in claim 1, wherein the IO isolation circuits are IO isolation latches.

10. A battery-powered device including an apparatus according to claim 1.

11. A mobile communications device including an apparatus according to claim 1, in which the apparatus comprises an integrated circuit.

12. A method of operating an integrated circuit comprising a processor, a controller and plural terminals, each terminal comprising a connection between the integrated circuit and a peripheral device, wherein each terminal interfaces to a logic circuit on the integrated circuit by a respective input/output IO cell in series connection with a respective IO isolation circuit, the method comprising, on power up of the integrated circuit:

entering a reset state;

subsequently releasing the reset state; and

subsequently releasing IO isolation by the IO isolation circuits.

14. A method as claimed in claim 12, wherein each IO isolation circuit is arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit.

15. A method as claimed in claim 12, wherein the IO isolation circuits are controllable by a software driver for a peripheral device connected to the terminal and associated with the IO isolation circuit.

16. A method as claimed in claim 12, wherein plural IO isolation circuits are connected so as to be commonly controllable by a single control signal from the controller.

17. A method as claimed in claim 12, wherein the IO isolation circuits are powered by an IO cell voltage supply.

18. A method as claimed in claim 12, wherein the integrated circuit comprises a respective voltage shifter circuit interposed between each IO cell and the corresponding IO isolation circuit.

19. A method as claimed in claim 12, wherein each IO isolation circuit is interposed between its corresponding IO cell and a respective voltage shifter circuit.

20. A method as claimed in claim 12, wherein the IO isolation circuits are IO isolation latches.

13. A memory storing machine readable instructions, which when executed by computing apparatus control it to perform a method of operating an integrated circuit comprising a processor, a controller and plural terminals, each terminal comprising a connection between the integrated circuit and a peripheral device, wherein each terminal interfaces to a logic circuit on the integrated circuit by a respective input/output IO cell in series connection with a respective IO isolation circuit,

the method comprising, on power up of the integrated circuit:

entering a reset state;

subsequently releasing the reset state; and

subsequently releasing IO isolation by the IO isolation circuits.