Systems, methods, and apparatuses for high power complementary metal oxide semiconductor (CMOS) antenna switches using body switching and substrate junction diode controlling in multistacking structure

• US 7,843,280 B2
• Filed: 11/20/2007
• Issued: 11/30/2010
• Est. Priority Date: 12/01/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Lee, Chang-Ho, Chang, Jaejoon, Kim, Haksun, Woo, Wangmyong, Laskar, Joy, Ahn, Minsik
• Primary Examiner(s): Takaoka; Dean O
• Application Number:
  US11/943,378
• Publication Number:
  US 20080129642A1
• Time in Patent Office: 1,106 Days
• Field of Search: 333/101, 333/103, 333/104, 333/262, 327/365, 327/534, 455/78
• US Class Current: 333/103
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a −60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Claims

1. A CMOS antenna switch, comprising:

an antenna operative at a plurality of radio frequency (RF) bands;

a transmit switch in communication with the antenna; and

a receiver switch in communication with the antenna, wherein the receiver switch includes a plurality of transistors, including a first transistor and a second transistor, wherein the first transistor includes a first source, a first drain, and a first body substrate, wherein the second transistor includes a second source, a second drain, and a second body substrate, wherein the first body substrate is electrically connected to the first source or the first drain, and wherein the second body substrate is selectively connectable between a resistance and ground, and wherein the plurality of transistors further includes a body substrate switch for selectively connecting the second body substrate between the resistance and ground.

2. The antenna switch of claim 1, wherein the first drain is connected to the second source, and wherein the second drain is connected to at least one receive block.

3. The antenna switch of claim 2, wherein the plurality of transistors comprises a third transistor having a third source, a third drain, and a third body substrate, wherein the third body substrate is electrically connected to the third source or the third drain, and wherein the third drain is electrically connected to the first source.

4. The antenna switch of claim 1, wherein the resistance includes an OFF-state resistance of the body substrate switch.

5. The antenna switch of claim 1, wherein the second body substrate includes a third source and a third drain, wherein the third source is connected to the second body substrate, and wherein the third drain is connected to ground.

6. The antenna switch of claim 1, wherein during a transmit (Tx) mode, the transmit switch is enabled, the receiver switch is disabled, and the body substrate switch is enabled to connect the second body substrate to ground, thereby minimizing leakage current for preventing channel formation in the receiver switch.

7. The antenna switch of claim 1, wherein during a receive (Rx) mode, the transmit switch is disabled, the receiver switch is enabled, and the body substrate switch is disabled to provide the resistance between the second body substrate and ground, thereby forming a signal path for a receive signal.

8. The antenna switch of claim 1, wherein the plurality of transistors comprise Complementary Metal Oxide Semiconductor (CMOS) transistors that are cascaded together.

9. The antenna switch of claim 1, wherein the first transistor having the first body substrate that is electrically connected to the first source or the first drain is nearest to the antenna.

10. A method for a CMOS antenna switch, comprising:

providing an antenna operative at a plurality of radio frequency bands;

electrically connecting a transmit switch and a receiver switch to the antenna, wherein the receiver switch comprises a plurality of transistors, including a first transistor and a second transistor, wherein the first transistor includes a first source, a first drain, and a first body substrate, and wherein the second transistor includes a second source, a second drain, and a second body substrate;

electrically connecting the first body substrate to the first source or the first drain; and

selectively connecting the second body substrate between a resistance and ground, wherein the second body substrate is selectively connected between a resistance and ground using a body substrate switch.

11. The method of claim 10, wherein the first drain is connected to the second source, and wherein the second drain is connected to at least one receive block.

12. The method of claim 11, wherein the plurality of transistors comprises a third transistor having a third source, a third drain, and a third body substrate, and further comprising:

electrically connecting the third body substrate to the third source or the third drain, and wherein the third drain is electrically connected to the first source.

13. The method of claim 10, wherein the resistance includes an OFF-state resistance of the body substrate switch.

14. The method of claim 10, wherein the second body substrate includes a third source and a third drain, wherein the third source is connected to the second body substrate, and wherein the third drain is connected to ground.

15. The method of claim 10, wherein during a transmit (Tx) mode, the transmit switch is enabled, the receiver switch is disabled, and the body substrate switch is enabled to connect the second body substrate to ground, thereby minimizing leakage current for preventing channel formation in the receiver switch.

16. The method of claim 10, wherein during a receive (Rx) mode, the transmit switch is disabled, the receiver switch is enabled, and the body substrate switch is disabled to provide the resistance between the second body substrate and ground, thereby forming a signal path for a receive signal.

17. The method of claim 10, wherein the plurality of transistors comprise Complementary Metal Oxide Semiconductor (CMOS) transistors that are cascaded together.

18. The method of claim 10, wherein the first transistor having the first body substrate that is electrically connected to the first source or the first drain is nearest to the antenna.