Power-on reset apparatus, systems, and methods

• US 7,843,316 B1
• Filed: 08/21/2007
• Issued: 11/30/2010
• Est. Priority Date: 03/19/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Khieu, Cong
• Primary Examiner(s): Bugg; George A
• Assistant Examiner(s): SMALL, NAOMI J
• Application Number:
  US11/842,862
• Time in Patent Office: 1,197 Days
• Field of Search: 340/10.1
• US Class Current: 340/10.1
• CPC Class Codes: G06F 1/24 Resetting means

Abstract

Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including processors, memories, and radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to the processing circuit of an RFID tag. Additional activity may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.

Claims

1. An integrated circuit chip, comprising:

an independent current circuit to provide a current substantially independent of a supply voltage;

a dependent current circuit to provide a current substantially dependent on the supply voltage; and

an output circuit to provide a power-on reset indication based on a comparison between the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

2. The integrated circuit chip of claim 1, wherein the independent current circuit comprises:

a transistor coupled directly to the supply-voltage.

3. The integrated circuit chip of claim 1, wherein the dependent current circuit comprises:

a transistor having a gate controlled by current that has a magnitude depending on a voltage across a transistor coupled to the supply voltage.

4. The integrated circuit chip of claim 3, wherein the voltage across the transistor comprises:

a source to drain voltage.

5. The integrated circuit chip of claim 1, comprising:

a transistor configured to bound a reference voltage coupled to a comparison of the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

6. The integrated circuit chip of claim 1, wherein the output circuit comprises:

a logic function circuit to receive the comparison of the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

7. The integrated circuit chip of claim 6, wherein the logic function circuit comprises:

a pair of serially-connected Schmitt triggers.

8. The integrated circuit chip of claim 1, comprising:

a first transistor and a second transistor, wherein the first transistor is in a first state when the supply voltage is less than a power-on selected value, wherein the first transistor is in a second state when the supply voltage is greater than the power-on selected value to permit charging a capacitor using current through the second transistor, and wherein the power-on reset indication is asserted responsive to the charging.

9. An article comprising a machine-readable memory containing thereon instructions which, if executed by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit will result on the wafer, comprising:

an independent current circuit to provide a current substantially independent of a supply voltage;

a dependent current circuit to provide a current substantially dependent on the supply voltage; and

an output circuit to provide a power-on reset indication based on a comparison between the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

10. The article of claim 9, in which the independent current circuit comprises:

a transistor coupled directly to the supply-voltage.

11. The article of claim 9, in which the dependent current circuit comprises:

a transistor having a gate controlled by current that has a magnitude depending on a voltage across a transistor coupled to the supply voltage.

12. The article of claim 9, wherein the voltage across the transistor comprises:

a source to drain voltage.

13. The article of claim 9, in which the integrated circuit further comprises:

a transistor configured to bound a reference voltage coupled to a comparison of the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

14. The article of claim 9, in which the output circuit comprises:

a logic function circuit to receive the comparison of the current substantially dependent on the supply voltage and the current substantially independent of the supply voltage.

15. The article of claim 9, in which the logic function circuit comprises:

a pair of serially-connected Schmitt triggers.

16. The article of claim 9, in which the integrated circuit further comprises:

a first transistor and a second transistor, wherein the first transistor is in a first state when the supply voltage is less than a power-on selected value, wherein the first transistor is in a second state when the supply voltage is greater than the power-on selected value to permit charging a capacitor using current through a second transistor, and wherein the power-on reset indication is asserted responsive to the charging.