Display apparatus with transistors connected to sub-pixel electrodes

• US 7,843,520 B2
• Filed: 11/20/2008
• Issued: 11/30/2010
• Est. Priority Date: 04/23/2008
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sung, Si-Duk, Kim, Sung-Woon, Kim, Hee-Seop, Lee, Seung-Hoon, Jung, Mee-Hye, Jung, Kwang-Chul, Ko, Chun-Seok, Lu, Jiangang
• Primary Examiner(s): WONG, TINA MEI SENG
• Application Number:
  US12/274,666
• Publication Number:
  US 20090268112A1
• Time in Patent Office: 740 Days
• Field of Search: None
• US Class Current: 349/38
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel

Abstract

A display apparatus includes a plurality of pixel regions. Each of the pixel regions includes a first sub-pixel region, a second sub-pixel region and a boost capacitor. The first sub-pixel region and the second sub-pixel region are electrically connected to the boost capacitor. The boost capacitor causes voltages the first and second sub-pixel regions to be at different voltages to increase the viewing angle of the display apparatus. One electrode of the boost capacitor, a coupling electrode, is formed over a storage capacitance line made of an opaque metal such that an additional boost capacitor (Cboost) may be formed without decreasing the aperture ratio of the pixel region. Other features are also provided.

Claims

1. A display apparatus comprising:

a first gate line and a second gate line;

a data line traversing the first and second gate lines;

a first sub-pixel electrode;

a first transistor connected to the first gate line, the data line, and the first sub-pixel electrode;

a second sub-pixel electrode;

a second transistor connected to the first gate line, the data line, and the second sub-pixel electrode;

a storage capacitance electrode;

a third transistor connected to the first gate line and the storage capacitance electrode;

a coupling electrode formed over the storage capacitance electrode, the coupling electrode overlapping the first sub-pixel electrode to form a boost capacitor; and

a fourth transistor connected to the second gate line, the coupling electrode and the second sub-pixel electrode.

2. The display apparatus of claim 1,

wherein the third transistor comprises a source electrode connected to the coupling electrode and a drain electrode connected to the storage capacitance electrode, and the fourth transistor comprises a source electrode connected to the coupling electrode and a drain electrode connected to the second sub-pixel electrode.

3. The display apparatus of claim 2,

wherein the drain electrode of the third transistor is connected to the storage capacitance electrode via a connecting electrode.

4. The display apparatus of claim 3,

wherein the drain electrode of the third transistor and the storage capacitance electrode are made of different metal layers.

5. The display apparatus of claim 3,

wherein the source electrode of the third transistor and the source electrode of the fourth transistor are made of the same metal layer.

6. The display apparatus of claim 1,

wherein the storage capacitance electrode overlaps the first sub-pixel electrode to form a first storage capacitor, and the storage capacitance electrode overlaps the second sub-pixel electrode to form a second storage capacitor.

7. The display apparatus of claim 5 further comprising:

a first auxiliary electrode forming the first storage capacitor with the storage capacitance electrode and connected to the first sub-pixel electrode through a first contact hole; and

a second auxiliary electrode forming the second storage capacitor with the storage capacitance electrode and connected to the second sub-pixel electrode through a second contact hole.

8. The display apparatus of claim 1,

wherein the storage capacitance electrode comprises a first portion overlapping the second sub-pixel electrode to form a second storage capacitor and a second portion having a narrower width than the first portion and overlapping the first sub-pixel electrode to form a first storage capacitor.

9. The display apparatus of claim 8 further comprising:

a third auxiliary electrode forming the second storage capacitor with the first portion of the storage capacitance electrode,

wherein the third auxiliary electrode is connected to the second sub-pixel electrode through a contact hole.

10. A method for manufacturing a display apparatus, the method comprising forming a first gate line;

a second gate line;

a data line traversing the first and second gate lines;

a first sub-pixel electrode;

a first transistor connected to the first gate line, the data line, and the first sub-pixel electrode;

a second sub-pixel electrode;

a second transistor connected to the first gate line, the data line, and the second sub-pixel electrode;

a storage capacitance electrode;

a third transistor connected to the first gate line and the storage capacitance electrode;

a coupling electrode formed over the storage capacitance electrode, the coupling electrode overlapping the first sub-pixel electrode to form a boost capacitor; and

a fourth transistor connected to the second gate line, the coupling electrode and the second sub-pixel electrode.

11. The method of claim 10,

wherein the third transistor comprises a source electrode connected to the coupling electrode and a drain electrode connected to the storage capacitance electrode, and the fourth transistor comprises a source electrode connected to the coupling electrode and a drain electrode connected to the second sub-pixel electrode.

12. The method of claim 11,

wherein the drain electrode of the third transistor is connected to the storage capacitance electrode via a connecting electrode.

13. The method of claim 12,

wherein the drain electrode of the third transistor and the storage capacitance electrode are made of different metal layers.

14. The method of claim 12,

wherein the source electrode of the third transistor and the source electrode of the fourth transistor are made of the same metal layer.

15. The method of claim 10,

wherein the storage capacitance electrode overlaps the first sub-pixel electrode to form a first storage capacitor, and the storage capacitance electrode overlaps the second sub-pixel electrode to form a second storage capacitor.

16. The method of claim 14 further comprising:

forming a first auxiliary electrode which forms the first storage capacitor with the storage capacitance electrode and connected to the first sub-pixel electrode through a first contact hole; and

forming a second auxiliary electrode forming the second storage capacitor with the storage capacitance electrode and connected to the second sub-pixel electrode through a second contact hole.

17. The method of claim 10,

wherein the storage capacitance electrode comprises a first portion overlapping the second sub-pixel electrode to form a second storage capacitor and a second portion having a narrower width than the first portion and overlapping the first sub-pixel electrode to form a first storage capacitor.

18. The method of claim 17 further comprising:

forming a third auxiliary electrode which forms the second storage capacitor with the first portion of the storage capacitance electrode,

wherein the third auxiliary electrode is connected to the second sub-pixel electrode through a contact hole.