Non-volatile memory devices including stacked NAND-type resistive memory cell strings and methods of fabricating the same

• US 7,843,718 B2
• Filed: 07/24/2008
• Issued: 11/30/2010
• Est. Priority Date: 07/26/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ha, Dae-Won, Koh, Gwan-Hyeob
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US12/178,962
• Publication Number:
  US 20090027955A1
• Time in Patent Office: 859 Days
• Field of Search: 365/148, 365/63, 365/158, 365/173
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

Claims

1. A non-volatile memory device, comprising:

a substrate;

an insulating layer on the substrate;

a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string; and

a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells,

wherein at least one of the plurality of resistive memory cells comprises;

a switching device including a body pattern comprising a source region, a channel region, and a drain region stacked in the insulating layer, and a gate electrode on a sidewall of the body pattern; and

a data storage element connected in parallel with the switching device, the data storage element comprising a lower electrode spaced apart from the body pattern of the switching device, a variable resistor on the lower electrode, and an upper electrode on the variable resistor,

wherein the upper electrode of the first one of the plurality of resistive memory cells is on the lower electrode and the body pattern of the next one of the plurality of resistive memory cells in the NAND type memory cell string.

2. The non-volatile memory device of claim 1, further comprising:

a bit line contact plug on the upper electrode of the last one of the plurality of resistive memory cells,

wherein the bit line is directly connected to the upper electrode of the last one of the plurality of resistive memory cells by the bit line contact plug.

3. The non-volatile memory device of claim 1, wherein the gate electrode of the switching device comprises a word line in the insulating layer extending substantially perpendicular to the bit line.

4. The non-volatile memory device of claim 1, wherein the variable resistor comprises a phase change material layer that is configured to transition between an amorphous state and a crystalline state responsive to heat applied thereto via the lower electrode.

5. The non-volatile memory device of claim 1, further comprising:

a main switching device on the substrate, wherein the main switching device is electrically connected to the first one of the plurality of resistive memory cells.

6. The non-volatile memory device of claim 5, wherein the main switching device comprises:

a main source region and a main drain region in the substrate; and

a main gate electrode on the substrate between the main source and the main drain region,

wherein the main drain region is electrically connected to the lower electrode and the body pattern of the first one of the plurality of resistive memory cells.

7. The non-volatile memory device of claim 1, wherein the gate electrode of the switching device is on opposing sidewalls of the body pattern.

8. The non-volatile memory device of claim 7, wherein the variable resistor and the lower electrode are confined within a contact hole in the insulating layer.

9. The non-volatile memory device of claim 8, further comprising:

an insulating spacer between sidewalls of the contact hole and the variable resistor.

10. A non-volatile memory device, comprising:

a substrate;

an insulating layer on the substrate;

a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string; and

a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells,

wherein at least one of the plurality of resistive memory cells comprises;

a switching device including a body pattern comprising a source region, a channel region, and a drain region stacked in the insulating layer, and a gate electrode on a sidewall of the body pattern;

a variable resistor spaced apart from the switching device; and

an upper electrode on the variable resistor and the drain region of the switching device, and

wherein the upper electrode of the first one of the plurality of resistive memory cells electrically connects the variable resistor and the drain region of the first one of the plurality of resistive memory cells with the variable resistor and the source region of the next one of the plurality of resistive memory cells in the NAND-type resistive memory cell string.

11. The non-volatile memory device of claim 10, wherein the variable resistor comprises one of a praseodymium calcium manganese oxide (PCMO) layer and a transition metal oxide layer.

12. The non-volatile memory device of claim 11, wherein the variable resistor comprises a magnetic tunnel junction (MTJ) structure including a pinned layer, a tunneling insulating layer and a free layer, which are sequentially stacked.

13. A method of fabricating a non-volatile memory device, the method comprising:

forming an insulating layer on a substrate;

forming a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define NAND-type resistive memory cell string; and

forming a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells,

wherein forming at least one of the plurality of resistive memory cells comprises;

forming an interlayer insulating layer on the substrate;

forming a switching device in the interlayer insulating layer including a body pattern comprising a source region, a channel region, and a drain region stacked in the interlayer insulating layer; and

forming a data storage element in the interlayer insulating later and electrically connected between the source region and the drain region of the switching device,

wherein forming the switching device comprises;

patterning the interlayer insulating layer to define an opening therein;

forming the body pattern in the opening in the interlayer insulating layer;

implanting impurity ions into the body pattern to define the source region, the channel region, and the drain region stacked in the opening in the interlayer insulating layer; and

forming a gate electrode on a sidewall of the body pattern.

14. The method of claim 13, wherein forming the gate electrode comprises:

etching the interlayer insulating layer to form a groove exposing the sidewall of the body pattern;

forming a gate insulating layer on the exposed sidewall of the body pattern; and

forming the gate electrode in the groove on the gate insulating layer.

15. The method of claim 13, further comprising the following before forming the insulating layer:

forming a main source region and a main drain region in the substrate; and

forming a main gate electrode on the substrate between the source region and the drain region to define a main switching device,

wherein forming the plurality of resistive memory cells comprises forming the first one of the plurality of resistive memory cells on the main switching device such that the source region thereof is electrically connected to the main drain region of the main switching device.

16. A method of fabricating a non-volatile memory device, the method comprising:

forming an insulating layer on a substrate;

forming a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define NAND-type resistive memory cell string; and

forming a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells,

wherein forming at least one of the plurality of resistive memory cells comprises;

forming an interlayer insulating layer on the substrate;

forming a switching device in the interlayer insulating layer including a body pattern comprising a source region, a channel region, and a drain region stacked in the interlayer insulating layer; and

forming a data storage element in the interlayer insulating later and electrically connected between the source region and the drain region of the switching device, wherein forming the data storage element comprises;

forming an opening extending through the interlayer insulating layer;

forming a lower electrode in the opening;

forming a variable resistor on the lower electrode; and

forming an upper electrode on the variable resistor,

wherein the upper electrode of the first one of the plurality of resistive memory cells is on the lower electrode and the body pattern of the next one of the plurality of resistive memory cells in the NAND-type resistive memory cell string.

17. The method of claim 16, wherein the variable resistor comprises a phase change material layer that is configured to transition between an amorphous state and a crystalline state responsive to heat applied thereto via the lower electrode.

18. The method of claim 16, further comprising:

forming a bit line contact plug on the upper electrode of the last one of the plurality of resistive memory cells,

wherein the bit line is directly connected to the upper electrode of the last one of the plurality of resistive memory cells by the bit line contact plug.

19. The method of claim 16, wherein forming the data storage element comprises:

forming the variable resistor on the lower electrode in the opening in the interlayer insulating layer such that the variable resistor is confined therein; and

forming the upper electrode on the variable resistor and the body pattern.

20. The method of claim 19, further comprising:

forming an insulating spacer on sidewalls of the opening in the interlayer insulating layer before forming the variable resistor therein.

21. A method of fabricating a non-volatile memory device, the method comprising:

forming an insulating layer on a substrate;

forming a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define NAND-type resistive memory cell string; and

forming a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells,

wherein forming at least one of the plurality of resistive memory cells comprises;

forming an interlayer insulating layer on the substrate;

forming a switching device in the interlayer insulating layer including a body pattern comprising a source region, re ion, a channel region, and a drain region stacked in the interlayer insulating layer; and

forming a data storage element in the interlayer insulating later and electrically connected between the source region and the drain region of the switching device, wherein forming the data storage element comprises;

forming a contact hole extending through the interlayer insulating layer;

forming a variable resistor in the hole; and

forming an upper electrode on the variable resistor and the body pattern.

22. The method of claim 21, wherein the variable resistor comprises one of a praseodymium calcium manganese oxide layer and a transition metal oxide layer.

23. The method of claim 21, wherein the variable resistor comprises a magnetic tunnel junction structure including a pinned layer, a tunneling insulating layer and a free layer, which are sequentially stacked.