Semiconductor memory device
First Claim
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1. A semiconductor memory device, comprising:
- an address buffering unit configured to buffer an input address;
a data input/output line configured to transfer data stored in a cell array;
a selecting unit configured to select, in response to operation modes of the device, one of the buffered input address and the transferred data as an output of the selecting unit and output the selected output; and
an output circuit configured to latch the selected output of the selecting unit as an output of the device.
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Abstract
A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.
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Citations
14 Claims
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1. A semiconductor memory device, comprising:
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an address buffering unit configured to buffer an input address; a data input/output line configured to transfer data stored in a cell array; a selecting unit configured to select, in response to operation modes of the device, one of the buffered input address and the transferred data as an output of the selecting unit and output the selected output; and an output circuit configured to latch the selected output of the selecting unit as an output of the device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory device, comprising:
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a selecting unit configured to select, in response to operation modes of the device, one of an output address received by the device and data stored in a cell array as an output of the selecting unit and output the selected output; and an output circuit configured to output from the device the selected output of the selecting unit. - View Dependent Claims (11, 12, 13, 14)
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Specification