High resolution time interpolator

• US 7,843,771 B2
• Filed: 12/14/2007
• Issued: 11/30/2010
• Est. Priority Date: 12/14/2007
• Status: Expired due to Fees

• Current Assignee: Guide Technology Inc. (GuideTech Incorporated)
• Original Assignee: Guide Technology Inc. (GuideTech Incorporated)
• Inventors: Tabatabaei, Sassan
• Primary Examiner(s): Miska; Vit W
• Application Number:
  US11/956,530
• Publication Number:
  US 20090154300A1
• Time in Patent Office: 1,082 Days
• Field of Search: 368/113, 368118-121, 327/27, 327/93, 702/79, 702/89, 702/176
• US Class Current: 368/118
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means
• CPC Class Codes: H03M 1/14 Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit

Abstract

The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Claims

1. A method for providing improved resolution in an interpolator, comprising:

providing an interpolator comprising a capacitor, a capacitor charging source, and an analog to digital converter;

applying a sampling charging current from the capacitor charging source to the capacitor to produce a voltage ramp across the capacitor;

sampling the voltage level across the capacitor with the analog to digital converter a plurality of times as the sampling charging current is applied;

processing the sampled voltage levels to increase measurement resolution of the capacitor voltage at the application of the sampling charging current; and

storing a value representing the processed sampled voltage levels.

2. The method of claim 1, wherein processing comprises averaging the plurality of sampled voltage levels.

3. The method of claim 1, further comprising:

applying an initializing charging current from the capacitor charging current source to the capacitor to produce a voltage across the capacitor;

sampling the voltage level across the capacitor with the analog to digital converter as the initializing charging current is applied;

processing the value of the voltage sample to derive a correction value reflecting settling as the initialization charging current is applied; and

storing the correction value based on the processed values.

4. The method of claim 1, further comprising:

applying a calibration signal to the interpolator;

applying a sampling charging current to the capacitor from the charging current source to produce a voltage across the capacitor;

sampling the voltage level across the capacitor with the analog to digital converter as the sampling charging current is applied;

processing the value of the voltage samples taken as the sampling charging current is applied to derive a calibration value; and

storing the calibration value based on the processed value.

5. The method of claim 4, wherein sampling the voltage level across the capacitor as the sampling charging current is applied comprises sampling the voltage level across the capacitor a plurality of times as the sampling charging current is applied.

6. The method of claim 5, wherein processing the value of the voltage samples taken as the sampling charging current is applied comprises averaging the plurality of samples.

7. The method of claim 6, further comprising:

creating and storing a calibration table based on the number of samples taken as the sampling charging current is applied and the averages values of the samples.

8. The method of claim 1, further comprising:

associating a temperature sensor with the interpolator;

heating the interpolator to a plurality of predetermined temperatures;

recording measurements from the temperature sensor; and

constructing and storing a temperature calibration table based on the recorded measurements and the predetermined temperatures.

9. A method for reducing settling error in an interpolator, comprising:

providing a capacitor;

providing a current mirror charging current source;

charging the capacitor from the current mirror charging current source for a first predetermined time;

providing an analog to digital converter;

sampling the voltage across the capacitor with the analog to digital converter during the first predetermined time;

processing the samples taken during the first predetermined time to derive a correction value;

discharging the capacitor during a measurement interval;

charging the capacitor from the current mirror charging current source during a sampling interval;

sampling the voltage across the capacitor with the analog to digital converter during the sampling interval; and

subtracting the correction value from the sampled values taken during the sampling interval,

whereby interpolated data values may be derived with reduced error resulting from settling voltages across the capacitor.

10. The method of claim 9, wherein sampling the voltage across the capacitor during the first predetermined time comprises sampling the voltage across the capacitor a plurality of times during the first predetermined time.

11. The method of claim 10, wherein processing the plurality of samples taken during the first predetermined time comprises averaging the plurality of samples.

12. The method of claim 11, wherein sampling the voltage across the capacitor during the sampling interval comprises sampling the voltage across the capacitor a plurality of times during the sampling interval.

13. The method of claim 12, further comprising:

averaging the plurality of samples taken during the sampling interval.