Storage gateway initiator for fabric-backplane enterprise servers

• US 7,843,906 B1
• Filed: 10/22/2005
• Issued: 11/30/2010
• Est. Priority Date: 02/13/2004
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Habanero Holdings Incorporated
• Inventors: Chidambaram, Sriram, Bhasin, Harinder Singh, Yeh, Jia-Jen, Abou-Emara, Akram A., Youngworth, Christopher Dean, Saraiya, Nakul Pratap
• Primary Examiner(s): Shah, Chirag G
• Assistant Examiner(s): Shivers, Ashley L
• Application Number:
  US11/256,645
• Time in Patent Office: 1,865 Days
• Field of Search: None
• US Class Current: 370/386
• CPC Class Codes: H04L 47/6205 Arrangements for avoiding head of line blocking
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/3045 Virtual queuing
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

Storage gateway remote and local access to storage devices is provided in part via an initiator implementing bandwidth-controlled access to the devices. The initiator may be iSCSI-compatible, and may also optionally implement protection, security, and performance features. The protection and security features include any combination of VLANs, zoning, Logical Unit Number (LUN) masking, and encryption. The performance features include any combination of HW-accelerated Remote Direct Memory Access (RDMA), prioritized I/O operations, and service priority (such as strict priority and straight or weighted round-robin priorities). An initiator may be implemented in a Processor Memory Module (PMM) coupled to a switch fabric that is in turn coupled to a target implemented in a Fibre Channel Module (FCM). Storage traffic may be communicated as Small Computer System Interface (SCSI)- and SCSI over Transmission Control Protocol/Internet Protocol (iSCSI)-compatible information (data and commands) on the switch fabric via cellifying input/output interface devices.

Claims

1. A system comprising:

a switch fabric having a plurality of physical ports;

a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition coupled to the switch fabric via at least one respective partition input/output controller, each physical partition comprising links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions;

wherein at least a first one of the physical partitions is enabled to execute a mass storage control process to control mass storage traffic, the mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;

wherein at least a second one of the physical partitions is enabled to execute a program to process the mass storage traffic; and

wherein the partition input/output controllers are enabled to communicate the mass storage traffic between a plurality of processes executing on the physical partitions and a mass storage input/output controller coupled to the switch fabric, at least in part by addressing cells to physical port addresses corresponding to physical ports of the switch fabric, and each of the partition and the mass storage input/output controllers is associated with a respective unique one of the physical ports.

2. The system of claim 1, wherein the input/output controllers comprise respective transmit-bandwidth-control circuits to control transmit bandwidth according to respective transmit bandwidth parameters.

3. The system of claim 2, wherein at least a portion of the transmit bandwidth parameters are determined by the mass storage control process.

4. The system of claim 1, wherein the input/output controllers comprise respective Direct Memory Access (DMA) circuits to access memory to communicate the mass storage traffic.

5. The system of claim 4, wherein at least a portion of the Direct Memory Access (DMA) circuits operate in accordance with parameters determined in part by the mass storage control process.

6. The system of claim 1, further comprising a mass storage interfacing unit coupled to the mass storage input/output controller.

7. The system of claim 6, further comprising a mass storage device coupled to the storage interfacing unit.

8. A non-transitory computer readable medium having a set of instructions stored therein which when executed by a computer causes the computer to perform functions comprising:

providing software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;

receiving initial mass storage system control information;

configuring a mass storage interface in accordance with the mass initial storage system control information, comprising communicating the mass initial storage system control information via a switch fabric;

accessing final mass storage system control information via the mass storage interface after the configuring of the mass storage interface;

reconfiguring the mass storage interface in accordance with the final mass storage system control information, comprising communicating the final mass storage system control information via the switch fabric; and

wherein the computer is one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition is enabled to communicate packets via at least one respective partition input/output controller coupled to a respective one of a plurality of physical ports of the switch fabric, the packet communicating is enabled at least in part by the respective partition input/output controller being enabled to send at least some of the packets as cells addressed to physical port addresses corresponding to the physical ports, and each physical partition comprises links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions.

9. The non-transitory computer readable medium of claim 8, wherein the functions further comprise requesting target names corresponding to storage targets accessible via the mass storage interface.

10. The non-transitory computer readable medium of claim 9, wherein the requesting of the target names is communicated to the mass storage interface via the switch fabric.

11. The non-transitory computer readable medium of claim 8, wherein the functions further comprise managing per-session target information corresponding to storage targets accessible via the mass storage interface.

12. The non-transitory computer readable medium of claim 8, wherein the mass storage interface is compatible with Fibre Channel (FC).

13. A method comprising:

in one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor, receiving initial mass storage system control information and in response determining a configuration of a mass storage interface in accordance with the initial mass storage system control information;

providing software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;

accessing final mass storage system control information via the mass storage interface after the determining of the mass storage interface configuration;

reconfiguring the mass storage interface in accordance with the final mass storage system control information, comprising communicating the final mass storage system control information via a switch fabric; and

wherein each physical partition is coupled to the switch fabric via at least one respective partition input/output controller coupled to a respective one of a plurality of physical ports of the switch fabric, the partition input/output controllers being enabled to communicate packets at least in part by sending at least some of the packets as cells addressed to physical port addresses corresponding to the physical ports, and each physical partition comprises links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions.

14. The method of claim 13, further comprising communicating mass storage data with the mass storage interface via the switch fabric.

15. The method of claim 14, wherein the mass storage data communicating is according to at least one of a bandwidth parameter and a priority parameter derived from the final mass storage system control information.

16. The method of claim 15, wherein at least one of the physical partitions comprises bandwidth-control circuitry responsive to the bandwidth parameter.

17. The method of claim 13, further comprising providing storage commands to the mass storage interface.

18. The method of claim 17, wherein at least a portion of the mass storage commands are Small Computer System Interface (SCSI) compatible commands.

19. The method of claim 17, wherein at least a portion of the mass storage commands are Small Computer System Interface (SCSI) over Transmission Control Protocol/Internet Protocol (iSCSI) compatible commands.

20. The method of claim 13, wherein the mass storage interface is compatible with a Fibre Channel (FC) device, the device being one of a disk drive, a tape drive, a tape library, a storage array, a storage switch, a storage director, a storage router, a storage network, and a storage area network (SAN).