Storage gateway target for fabric-backplane enterprise servers

• US 7,843,907 B1
• Filed: 10/22/2005
• Issued: 11/30/2010
• Est. Priority Date: 02/13/2004
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Habanero Holdings Incorporated
• Inventors: Abou-Emara, Akram A., Chidambaram, Sriram, Yeh, Jia-Jen, Bhasin, Harinder Singh, Youngworth, Christopher Dean, Saraiya, Nakul Pratap
• Primary Examiner(s): Shah, Chirag G
• Assistant Examiner(s): Shivers, Ashley L
• Application Number:
  US11/256,688
• Time in Patent Office: 1,865 Days
• Field of Search: None
• US Class Current: 370/386
• CPC Class Codes: H04L 47/6205 Arrangements for avoiding head of line blocking
• CPC Class Codes: H04L 49/3045 Virtual queuing
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

Storage gateway remote and local access to storage devices is provided in part via a target implementing bandwidth-controlled access to the devices. The target may be iSCSI-compatible, and may also optionally implement protection, security, and performance features. The protection and security features include any combination of VLANs, zoning, Logical Unit Number (LUN) masking, and encryption. The performance features include any combination of HW-accelerated Remote Direct Memory Access (RDMA), prioritized I/O operations, and service priority (such as strict priority and straight or weighted round-robin priorities). An initiator may be implemented in a Processor Memory Module (PMM) coupled to a switch fabric that is in turn coupled to a target implemented in a Fibre Channel Module (FCM). Storage traffic may be communicated as Small Computer System Interface (SCSI)- and SCSI over Transmission Control Protocol/Internet Protocol (iSCSI)-compatible information (data and commands) on the switch fabric via cellifying input/output interface devices.

Claims

1. A method comprising:

in one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor, initiating a mass storage session with a selected mass storage interface, the selected mass storage interface being coupled to the physical partitions via a switch fabric, the mass storage session at least in part via a mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;

accessing storage data via the selected mass storage interface in response to requests from the one of the physical partitions, the storage data being communicated in part via the switch fabric; and

wherein the selected mass storage interface comprises a mass storage input/output controller, each physical partition comprises at least one respective partition input/output controller, each physical partition is formed at least in part by programmatically configuring links between processors of the physically partitionable symmetric multiprocessor to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis, and each of the input/output controllers is associated with one of a plurality of physical ports of the switch fabric and enabled to provide cellifying transport via the switch fabric at least in part by addressing cells to a particular one of the physical ports.

2. The method of claim 1, wherein the one of the physical partitions is a first one of the physical partitions, the mass storage session is a first mass storage session, and further comprising in a second one of the physical partitions, initiating a second mass storage session with the selected mass storage interface.

3. The method of claim 2, further comprising in the second one of the physical partitions, initiating a third mass storage session with the selected mass storage interface.

4. The method of claim 3, further comprising, in the selected mass storage interface, managing respective per-session data corresponding to each of the mass storage sessions.

5. The method of claim 1, further comprising ceasing the mass storage session.

6. The method of claim 5, wherein the mass storage session is a first mass storage session, the selected mass storage interface is a first selected mass storage interface, and further comprising, in the one of the physical partitions, initiating a second mass storage session with a second selected mass storage interface.

7. The method of claim 5, wherein the one of the physical partitions is a first one of the physical partitions, the mass storage session is a first mass storage session, the selected mass storage interface is a first selected mass storage interface, and further comprising, in a second one of the physical partitions, initiating a second mass storage session with a second selected mass storage interface.

8. The method of claim 1, wherein the selected mass storage interface is compatible with a Fibre Channel (FC) device, the device being one of a disk drive, a tape drive, a tape library, a storage array, a storage switch, a storage director, a storage router, a storage network, and a storage area network (SAN).

9. A system comprising:

a switch fabric having a plurality of physical ports;

a mass storage interfacing element coupled to the switch fabric via a mass storage input/output controller;

a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition coupled to the switch fabric via at least one respective partition input/output controller, each physical partition comprising links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis;

wherein the mass storage interfacing element is enabled to execute a mass storage control process to control mass storage traffic, the mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces; and

wherein each of the input/output controllers is associated with a unique one of the physical ports of the switch fabric, and the input/output controllers are enabled to communicate the mass storage traffic between a plurality of processes executing on the physical partitions and the mass storage input/output controller at least in part by addressing cells to a particular one of the physical ports.

10. The system of claim 9, wherein the input/output controllers comprise respective transmit-bandwidth-control circuits to control transmit bandwidth according to respective transmit bandwidth parameters.

11. The system of claim 10, wherein at least a portion of the transmit bandwidth parameters are determined by the mass storage control process.

12. The system of claim 9, wherein the input/output controllers comprise respective Direct Memory Access (DMA) circuits to access memory to communicate the mass storage traffic.

13. The system of claim 12, wherein at least a portion of the Direct Memory Access (DMA) circuits operate in accordance with parameters determined in part by the mass storage control process.

14. The system of claim 9, further comprising a mass storage coupling unit included in the mass storage interfacing element and coupled to the mass storage input/output controller.

15. The system of claim 14, further comprising a mass storage device coupled to the mass storage coupling unit.

16. A non-transitory computer readable medium having a set of instructions stored therein which when executed by a computer causes the computer to perform functions comprising:

providing software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;

providing initial mass storage system control information to one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor via a switch fabric;

configuring a mass storage interface in accordance with the initial mass storage system control information, comprising receiving the initial mass storage system control information from the switch fabric;

accessing final mass storage system control information via the mass storage interface after the configuring of the mass storage interface;

reconfiguring the mass storage interface in accordance with the final mass storage system control information, comprising receiving the final mass storage system control information from the switch fabric;

wherein each physical partition is formed at least in part by programmatically configuring links between processors of the physically partitionable symmetric multiprocessor to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis; and

wherein the computer is included in the mass storage interface.

17. The non-transitory computer readable medium of claim 16, wherein the functions further comprise providing target names corresponding to storage targets accessible via the mass storage interface.

18. The non-transitory computer readable medium of claim 17, wherein the target names are communicated from the mass storage interface via the switch fabric.

19. The non-transitory computer readable medium of claim 16, wherein the functions further comprise managing per-channel information corresponding to channels initiated by processes executing on the physical partitions.

20. The non-transitory computer readable medium of claim 16, wherein the mass storage interface is compatible with Fibre Channel (FC).