Parallel interface bus to communicate video data encoded for serial data links

• US 7,844,762 B2
• Filed: 01/31/2007
• Issued: 11/30/2010
• Est. Priority Date: 02/24/2006
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Wolf, Paul D., Banks, John D.
• Primary Examiner(s): Tsai; Henry W
• Assistant Examiner(s): Sun; Michael
• Application Number:
  US11/669,416
• Publication Number:
  US 20070200859A1
• Time in Patent Office: 1,399 Days
• Field of Search: None
• US Class Current: 710/62
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/85 on discs or drums

Abstract

In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used to represent a pixel such that pixels are represented in more than one of the parallel groups. The parallel sink is to receive the parallel groups of signals from the bus, wherein the parallel sink includes a signal extractor to separate at least a portion of the groups of signals into multiple channels, and encoder and serializer circuits to encode and serialize the separated signals. Other embodiments are described and claimed.

Claims

1. A device comprising:

a parallel bus having a plurality of lanes;

a parallel source to provide parallel groups of signals including groups of video signals representing pixels and groups of control signals to the parallel bus, wherein the parallel bus has a number of lanes that is fewer than a number of signals used to represent a pixel, the parallel source including;

a signal divider to divide a video signal into a two or more subsets of signals, each subset including a number of bits that is no more than the number of bus lanes, the signal divider including a clock edge synchronizer to configurable to synchronize a plurality of subsets of signals in a clock cycle, the bits of each subset being synchronized to an edge of a clock signal, and

a controller to direct routing of video signals and control signals onto the parallel bus; and

a parallel sink to receive the parallel subsets of signals from the parallel bus, wherein the parallel sink includes;

a signal extractor to reconstruct the groups of signals from the received subsets of signals, the signal extractor to separate at least a portion of the groups of signals into multiple channels,

encoder and serializer circuits to encode and serialize the separated signals, the signal extractor being operable to re-time each group of signals such that the bits of each group of signals pass to the encoder and serializer circuits in the same clock cycle, and

a controller to control the receipt and extraction of signals.

2. The device of claim 1, wherein the parallel source is a parallel transition minimized differential signaling (TMDS)-based source and the parallel groups of signals are TMDS signals.

3. The device of claim 1, wherein the parallel bus has twelve lanes and twenty-four signals are used to represent a pixel.

4. The device of claim 1, wherein the signal extractor is to separate the at least a portion of the groups of signals into three color groups:

red, green, and blue.

5. The device of claim 1, wherein the parallel source is in a first chip and the parallel sink is in a second chip.

6. The device of claim 5, wherein the first chip includes video processing circuitry to provide the video signals to the parallel source, and the second chip is a physical layer (PHY) chip.

7. The device of claim 1, wherein the parallel source is a parallel video and audio source in which the group of signals include video, audio, and control signals, and the parallel sink is a parallel video and audio sink.

8. The device of claim 7, wherein the parallel source includes a signal formatter to format the video, audio, and control signals in a High-Definition Multimedia Interface (HDMI) compatible format, and a transmitter to transmit the video, audio, and control signals on the parallel bus.

9. The device of claim 1, wherein the device includes a DVD player.

10. The device of claim 1, wherein the signal extractor is to recreate at least one control signal that can be inferred from transmitted control signals.

11. A system comprising:

a serial link in a cable;

a system video and audio sink device;

a system video and audio source device coupled to the system video and audio sink device through a parallel bus, the system video and audio source device including;

a parallel source to provide parallel groups of signals including video signals and control signals to the parallel bus, wherein the parallel bus has a number of lanes that is fewer than a number of signals used to represent a pixel, the parallel source including;

a signal divider to divide a video signal into a two or more subsets of signals, each subset including a number of bits that is no more than the number of bus lanes, the signal divider including a clock edge synchronizer to configurable to synchronize a plurality of subsets of signals in a clock cycle, the bits of each subset being synchronized to an edge of a clock signal, and

a controller to direct routing of video signals and control signals onto the parallel bus; and

a parallel sink to receive the parallel subsets of signals from the parallel bus, wherein the parallel sink includes;

a signal extractor to reconstruct the groups of signals from the received subsets of signals, the signal extractor to separate at least a portion of the groups of signals into multiple channels,

encoder and serializer circuits to encode and serialize the separated signals, the signal extractor being operable to re-time each group of signals such that the bits of each group of signals pass to the encoder and serializer circuits in the same clock cycle, and

a controller to control the receipt and extraction of signals.

12. The system of claim 11, wherein the parallel source is a parallel transition minimized differential signaling (TMDS)-based source and the parallel groups of signals are TMDS signals.

13. The system of claim 11, wherein the parallel source is in a first chip and the parallel sink is in a second chip, wherein the parallel source is a parallel video and audio source in which the group of signals include video, audio, and control signals, and the parallel sink is a parallel video and audio sink, and wherein the first chip includes video processing circuitry to provide the video signals to the parallel video and audio source.

14. The system of claim 11, wherein the parallel source is a parallel video and audio source in which the group of signals include video, audio, and control signals, and the parallel sink is a parallel video and audio sink, and wherein the parallel source includes a signal formatter to format the video, audio, and control signals in a High-Definition Multimedia Interface (HDMI) compatible format, and a transmitter to transmit the video, audio, and control signals on the parallel bus.

15. The system of claim 11, wherein the system video and audio sink device is a high definition display, and the system video and audio source device is one of the following:

a DVD player, a set top box, and a computer.

16. A repeater for regenerating encoded signals for transmission over one or more serial links, the repeater comprising:

one or more inbound serial data links;

one or more parallel sources configured to encoded signals from said one or more inbound serial data links, and further configured to generate parallel encoded signals, each parallel source including;

a signal divider to divide a video signal into a two or more subsets of signals, each subset including a number of bits that is no more than a number of bus lanes of a parallel bus, the signal divider including a clock edge synchronizer to configurable to synchronize a plurality of subsets of signals in a clock cycle, the bits of each subset being synchronized to an edge of a clock signal, and

a controller to direct routing of video signals and control signals onto the parallel bus; and

one or more parallel sinks configured to extract groups of bits from said parallel TMDS-based signals, and further configured to serialized said groups of bits for transmission over said one or more serial links, each parallel sink including;

a signal extractor to reconstruct the groups of signals from the received subsets of signals, the signal extractor to separate at least a portion of the groups of signals into multiple channels,

encoder and serializer circuits to encode and serialize the separated signals, the signal extractor being operable to re-time each group of signals such that the bits of each group of signals pass to the encoder and serializer circuits in the same clock cycle, and

a controller to control the receipt and extraction of signals; and

one or more parallel buses for carrying said parallel encoded signals from said one or more parallel sources to said one or more parallel sinks, each of the parallel buses having a number of lanes that is fewer than a number of signals used to represent a pixel.

17. The repeater of claim 16, wherein said parallel encoded signals are transition-minimized differential signaling (“

TMDS”

) signals.

18. The repeater of claim 16, wherein said repeater is a High-Definition Multimedia Interface (“

HDMI”

) repeater and said one or more parallel TMDS-based buses are parallel HDMI buses.