Differential data transfer for flash memory card

• US 7,844,763 B2
• Filed: 10/29/2009
• Issued: 11/30/2010
• Est. Priority Date: 02/12/2004
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Lee, Charles C., Yu, I-Kang, Chou, Szu-Kuang, Chou, Horng-Yee
• Primary Examiner(s): CHEN, ALAN S
• Application Number:
  US12/608,842
• Publication Number:
  US 20100049878A1
• Time in Patent Office: 397 Days
• Field of Search: None
• US Class Current: 710/62
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06K 19/07732 the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks housings for electrical equipment in general, see H05K5/02
• CPC Class Codes: G06K 19/07733 the record carrier containing at least one further contact interface not conform ISO-7816
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

Claims

1. A flash memory card comprising:

a predetermined pin assignment based on a pin count of the flash memory card, the pin assignment including a set of pins for connected to two pairs of differential serial data lines, wherein each pair of the differential serial data lines carry a positive (+) signal and a negative (−

) signal;

a flash memory array;

a protocol controller for accessing the flash memory array; and

a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises;

a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and

a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises;

a synchronization detector for identifying a synchronization field in the first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal;

a write first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal;

a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal;

a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector;

a start-of-frame (SOF) detector for detecting SOF fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and

an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the write FIFO, the CRC detector, the command/data detector, and the SOF detector;

wherein the flash memory card comprises one of a MultiMediaCard, a Secure-Digital card, a CompactFlash card, and a Memory Stick.

2. An electronic device comprising:

a host card adapter for interfacing with the flash memory card, the host card adapter comprising a predetermined pin assignment based on a pin count of the flash memory card, the pin assignment including a set of pins for connecting to two pairs of differential serial data lines, wherein each pair of the differential serial data lines carry a positive (+) signal and a negative (−

) signal;

a protocol controller;

an application adapter for controlling the protocol controller, the application adapter providing a bridge between device-specific communications and card-specific communications;

a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises;

a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and

a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises;

a synchronization detector for identifying a synchronization field in the first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal;

a read first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal;

a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal;

a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector;

a start-of-frame (SOF) detector for detecting SOF fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and

an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the read FIFO, the CRC detector, and the command/data detector;

wherein the flash memory card comprises one of a MultimediaCard, a Secure-Digital card, a CompactFlash card and a Memory-Stick.

3. A method of performing an operation on a flash memory card, the operation being requested by a host platform, which is separate from the flash memory card, the operation using a set of pins for connecting to two pairs of differential serial data lines, wherein each pair of the differential serial data lines carry a positive (+) signal and a negative (−

) signal, the method comprising;

sending commands from the host platform to the flash memory card;

recognizing the flash memory card;

initializing the protocol of the flash memory card;

controlling the initializing and providing a bridge between device-specific communications and card-specific communications;

converting an incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into an outgoing differential signal; and

converting the incoming multipurpose serial signal into at least one of a status signal and an incoming data signal, and for converting at least one of a control signal and an outgoing data signal into the outgoing multipurpose serial signal;

identifying a synchronization field in a first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal;

storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal;

performing a cyclic redundancy check (CRC) check on the first set of signals in response to the start signal;

determining whether the first set of signals are one of command signals and data signals in response to the start signal and using that determination when performing the CRC check;

detecting start-of-frame (SOF) fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and

detecting an end-of-packet (EOP) field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to storing the first set of signals, performing the CRC check, and determining whether the first set of signals are one of command signals and data signals.