Data processing device and method

• US 7,844,796 B2
• Filed: 08/30/2004
• Issued: 11/30/2010
• Est. Priority Date: 03/05/2001
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Thomas, Alexander
• Primary Examiner(s): Treat; William M
• Application Number:
  US10/570,173
• Publication Number:
  US 20070113046A1
• Time in Patent Office: 2,283 Days
• Field of Search: 712/18
• US Class Current: 712/18
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Claims

1. A processing device comprising:

a configurable global interconnect structure including a plurality of multi-bit wide interconnects;

a plurality of configurable coarse grained elements; and

at least one dedicated multi-bit wide interconnect that is separate from the configurable global interconnect structure, each of the at least one dedicated multi-bit wide interconnect dedicated for connecting a respective single pair of the plurality of coarse grained elements;

wherein;

each of the coarse grained elements is connected to the global interconnect structure;

the plurality of coarse grained elements are arranged in rows, the rows being interconnected via the global interconnect structure; and

each of at least one of the plurality of coarse grained elements;

(a) includes;

at least one operand data input that is directly and vertically connected via a first one of the at least one dedicated multi-bit wide interconnect to a result data output of a respective first other one of the plurality of coarse grained elements; and

at least one result data output that is directly and vertically connected via a second one of the at least one dedicated multi-bit wide interconnect to an operand data input of a respective second other one of the plurality of coarse grained elements; and

(b) is on a different row than the first and second other ones of the plurality of coarse grained elements; and

(c) is adapted to transfer data from its respective at least one operand data input through units for processing multi-bit arithmetic functions, at least one multiplexer downstream of the units for processing multi-bit arithmetic functions, and at least one register downstream of the at least one multiplexer, to its respective at least one result data output.

2. The processing device according to claim 1, wherein at least two input/output connects to the global interconnect structure are provided in one row and wherein at least one of (a) a switch in the global interconnect structure and (b) one of a gate, buffer, and multiplexer is provided between the at least two input/output connects.

3. The processing device according to claim 1, wherein the each of the at least one of the plurality of coarse grained elements, its respective first other one of the plurality of coarse grained elements, and its respective second other one of the plurality of coarse grained elements are arranged in three successive rows.