Layered chip package and method of manufacturing same

• US 7,846,772 B2
• Filed: 06/23/2008
• Issued: 12/07/2010
• Est. Priority Date: 06/23/2008
• Status: Expired due to Fees

• Current Assignee: Headway Technologies Incorporated, TDK Corporation
• Original Assignee: Headway Technologies Incorporated, TDK Corporation
• Inventors: Ito, Hiroyuki, Sueki, Satoru, Harada, Tatsuya, Sasaki, Yoshitaka, Okuzawa, Nobuyuki
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): WHALEN, DANIEL B
• Application Number:
  US12/213,645
• Publication Number:
  US 20090315189A1
• Time in Patent Office: 897 Days
• Field of Search: 438/106, 438/108, 438/109, 257/686, 257/E23.085, 298/29, 292/30
• US Class Current: 438/109
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.

Claims

1. A method of manufacturing a layered chip package, the layered chip package comprising:

a main body having a top surface, a bottom surface and four side surfaces; and

a wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes;

a semiconductor chip having a top surface, a bottom surface and four side surfaces;

an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;

each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions,

the method comprising the steps of;

fabricating a plurality of substructures that respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and

completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body,

wherein the step of fabricating the plurality of substructures includes, as a series of steps for fabricating each substructure,

the step of fabricating a pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;

the step of forming at least one groove in the pre-substructure wafer, the at least one groove opening at the first surface of the pre-substructure wafer and extending to be adjacent to at least one of the pre-semiconductor-chip portions;

the step of forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and

the step of forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer,

wherein, in the step of completing the layered chip package, the insulating layer is cut to form a cut surface along a direction in which the at least one groove extends, whereby part of the at least one end face of the insulating portion is formed by the cut surface of the insulating layer and the end faces of the plurality of electrodes are exposed.

2. The method of manufacturing the layered chip package according to claim 1, wherein the step of completing the layered chip package includes the steps of:

fabricating a main body aggregate by using the plurality of substructures, the main body aggregate including a plurality of pre-main-body portions each of which will later become the main body, the plurality of pre-main-body portions being aligned in one direction that is orthogonal to a stacking direction of the plurality of layer portions;

forming the wiring for each of the pre-main-body portions of the main body aggregate; and

cutting the main body aggregate after the formation of the wiring so as to separate the plurality of pre-main-body portions from each other so that each of them becomes the main body and a plurality of layered chip packages are thereby formed.

3. The method of manufacturing the layered chip package according to claim 2, wherein the step of fabricating the main body aggregate includes the steps of:

fabricating a layered substructure by stacking the plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package; and

cutting the layered substructure so as to form the main body aggregate,

wherein the insulating layer is cut in the step of cutting the layered substructure.

4. The method of manufacturing the layered chip package according to claim 3, wherein:

in the step forming the plurality of electrodes, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of fabricating the layered substructure, alignment of the plurality of substructures to be stacked is performed using the alignment mark.

5. The method of manufacturing the layered chip package according to claim 4, wherein the insulating layer is transparent.

6. The method of manufacturing the layered chip package according to claim 3, wherein:

in the step of forming the at least one groove in the pre-substructure wafer, the at least one groove is formed to have a bottom that does not reach the second surface of the pre- substructure wafer; and

the step of fabricating the layered substructure includes the step of polishing each of the plurality of substructures from a surface corresponding to the second surface of the pre- substructure wafer until the at least one groove becomes exposed.

7. The method of manufacturing the layered chip package according to claim 2, wherein the step of fabricating the main body aggregate includes the steps of:

forming a plurality of elements by cutting each of the plurality of substructures, the plurality of elements being intended to be stacked later to thereby constitute the main body aggregate; and

stacking the plurality of elements so as to form the main body aggregate,

wherein the insulating layer is cut in the step of forming the plurality of elements.

8. The method of manufacturing the layered chip package according to claim 7, wherein:

in the step of forming the plurality of electrodes, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of stacking the plurality of elements, alignment of the plurality of elements to be stacked is performed using the alignment mark.

9. The method of manufacturing the layered chip package according to claim 8, wherein the insulating layer is transparent.

10. The method of manufacturing the layered chip package according to claim 2, wherein, in the step of forming the wiring, a plurality of the main body aggregates are arranged in the stacking direction of the plurality of layer portions and then the wiring is formed for each of the pre-main-body portions of the plurality of main body aggregates.

11. The method of manufacturing the layered chip package according to claim 10, wherein:

in the step of forming the plurality of electrodes, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of forming the wiring, alignment of the plurality of main body aggregates to be arranged in the stacking direction of the plurality of layer portions is performed using the alignment mark.

12. The method of manufacturing the layered chip package according to claim 11, wherein the insulating layer is transparent.

13. The method of manufacturing the layered chip package according to claim 1, wherein only one of the four side surfaces of the semiconductor chip is covered with the insulating portion while the other three of the four side surfaces of the semiconductor chip are respectively located at three of the side surfaces of the main body.

14. The method of manufacturing the layered chip package according to claim 1, wherein, of the four side surfaces of the semiconductor chip, two that face toward opposite directions are covered with the insulating portion while the other two are respectively located at two of the side surfaces of the main body.

15. The method of manufacturing the layered chip package according to claim 1, wherein:

the four side surfaces of the semiconductor chip are covered with the insulating portion; and

in the step of forming the at least one groove in the pre-substructure wafer, a plurality of first grooves and a plurality of second grooves are formed, the first and second grooves extending in directions orthogonal to each other.